Inventor

CHANG KUO-CHIN

TW38 patents

⚠️ This page may combine multiple inventors who share the name “CHANG KUO-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG KUO-CHIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-layer passivation structure and method

Semiconductor structure with polyimide packaging and manufacturing method

Shielding structures

Semiconductor device structure with bonding pad and method for forming the same

Semiconductor structure having a conductive bump with a plurality of bump segments

Semiconductor structure and manufacturing method thereof

Semiconductor device with bump structure and method of making semiconductor device

Semiconductor structure and manufacturing method thereof

Shielding structures

Shielding structures

Semiconductor structure and method of manufacturing the same

Semiconductor die

MIMcap corner structures in the keep-out zones of a semiconductor die and methods of forming the same

Semiconductor device

Semiconductor device

Semiconductor die

Semiconductor structure having counductive bump with tapered portions and method of manufacturing the same

Chip package structure with heat conductive layer

Package structure having lid with protrusion and manufacturing method thereof

Method for forming chip package structure with heat conductive layer

Semiconductor devices and methods of manufacture

Semiconductor device having a conductive via structure

Method of forming semiconductor device having a conductive via structure

Stacked via structures and methods for forming the same

Stacking via configuration for advanced silicon node products and methods for forming the same

Chip structure and method for forming the same

TAIWAN SEMICONDUCTOR MFG

Enhanced copper posts for wafer level chip scale packaging

Enhanced copper posts for wafer level chip scale packaging

Silicon-based thin substrate and packaging schemes

Protected solder ball joints in wafer level chip-scale packaging

Constraint stiffener design

Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging

WANG CHUNG YU

Protected solder ball joints in wafer level chip-scale packaging

LIN WEN-YI

Lid design for reliability enhancement in flip chip package

LU SZU-WEI

Silicon-based thin substrate and packaging schemes

LU SZU WEI

Silicon-based thin substrate and packaging schemes

LIN TSUNG-SHU

Method and structure for controlling package warpage

CHANG KUO-CHIN

Conductive via structure