Inventor

NARAYAN CHANDRASEKHAR

US74 patents

⚠️ This page may combine multiple inventors who share the name “NARAYAN CHANDRASEKHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYAN CHANDRASEKHAR

IBM

Chip and wafer integration process using vertical connections

Fuse processing using dielectric planarization pillars

High density chip carrier with integrated passive devices

High density chip carrier with integrated passive devices

Device to monitor and control the temperature of electronic chips to enhance reliability

Copper recess process with application to selective capping and electroless plating

Chip and wafer integration process using vertical connections

Defect management engine for semiconductor memories and memory systems

Conductor-insulator-conductor structure

Flat panel display containing black matrix polymer

Sealed DASD having humidity control and method of making same

Method for fabricating multi-layer thin film structure having a separation layer

Electronic structures having a joining geometry providing reduced capacitive loading

Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal

Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal

Multi-layer thin film structure and parallel processing method for fabricating same

Chip and wafer integration process using vertical connections

Chip and wafer integration process using vertical connections

Reprogrammable electrical fuse

TFT LCD active data line repair

Damascene anti-fuse with slot via

Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells

Thermoformed three dimensional wiring module

Seedless wirebond pad plating

Copper recess process with application to selective capping and electroless plating

Fuse structure and method to form the same

Crack stop between neighboring fuses for protection from fuse blow damage

Diffusion bonding of lead interconnections using precise laser-thermosonic energy

X-ray mask pellicle

Mechanical packaging and thermal management of flat mirror arrays

Mechanical packaging and thermal management of flat mirror arrays

Multilayered metallurgical structure for an electronic component

Manufacturing of cavity fuses on gate conductor level

Line level air gaps

Mixed fuse technologies

Structure and method for reducing thermo-mechanical stress in stacked vias

Fuse structure and method to form the same

Variable resistor structure and method for forming and programming a variable resistor for electronic circuits

Integrated circuits having reduced stress in metallization

Method for activating fusible links on a circuit substrate

Method for reducing stress in the metallization of an integrated circuit

Damage-free self-limiting through-substrate laser ablation

Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter

INFINEON TECHNOLOGIES CORP

Electrical fuses employing reverse biasing to enhance programming

Vertical fuse and method of fabrication

Vertical fuse and method of fabrication

INFINEON TECHNOLOGIES AG

System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient

Metal wire fuse structure with cavity

SIEMENS AG

Electrical fuses with tight pitches and method of fabrication in semiconductors

MODHA DHARMENDRA S

Electronic synapse