P

Inventor

KIEWRA EDWARD W

US43 patents
⚠️ This page may combine multiple inventors who share the name “KIEWRA EDWARD W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

28 patents
US6383920B1May 7, 2002

Process of enclosing via for improved reliability in dual damascene interconnects

IBM179 citations98
US6420749B1Jul 16, 2002

Trench field shield in trench isolation

IBM48 citations93
US7560375B2Jul 14, 2009

Gas dielectric structure forming methods

IBM34 citations92
US7102204B2Sep 5, 2006

Integrated SOI fingered decoupling capacitor

IBM24 citations92
US6486526B1Nov 26, 2002

Crack stop between neighboring fuses for protection from fuse blow damage

IBM42 citations92
US7964896B2Jun 21, 2011

Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics

IBM13 citations84
US7129557B2Oct 31, 2006

Autonomic thermal monitor and controller for thin film devices

IBM11 citations83
US6380027B2Apr 30, 2002

Dual tox trench dram structures and process using V-groove

IBM10 citations74
US10103280B1Oct 16, 2018

Rapid melt growth photodetector

IBM3 citations73
US9343545B2May 17, 2016

Electrical coupling of memory cell access devices to a word line

IBM3 citations73
US7674675B2Mar 9, 2010

Method of forming an integrated SOI fingered decoupling capacitor

IBM7 citations73
US7078259B2Jul 18, 2006

Method for integrating thermistor

IBM7 citations73
US6268638B1Jul 31, 2001

Metal wire fuse structure with cavity

IBM8 citations73
US9678273B2Jun 13, 2017

Device for propagating light and method for fabricating a device

IBM3 citations72
US9658400B2May 23, 2017

Method for fabricating a device for propagating light

IBM3 citations72
US9304335B2Apr 5, 2016

Integrated LDMOS devices for silicon photonics

IBM2 citations63
US9036959B2May 19, 2015

Intergrating a silicon photonics photodetector with CMOS devices

IBM3 citations63
US7287325B2Oct 30, 2007

Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing

IBM3 citations63
US11143953B2Oct 12, 2021

Protection of photomasks from 193nm radiation damage using thin coatings of ALD Al2O3

IBM0 citations61
US9882021B2Jan 30, 2018

Planar III-V field effect transistor (FET) on dielectric layer

IBM0 citations52
US9299804B2Mar 29, 2016

Electrical coupling of memory cell access devices to a word line

IBM1 citations52
US9287115B2Mar 15, 2016

Planar III-V field effect transistor (FET) on dielectric layer

IBM1 citations52
US8809860B2Aug 19, 2014

III-V compound semiconductor material passivation with crystalline interlayer

IBM1 citations52
US9691812B2Jun 27, 2017

Photodetector and methods of manufacture

IBM0 citations51
US7361584B2Apr 22, 2008

Detection of residual liner materials after polishing in damascene process

IBM0 citations51
US9590001B2Mar 7, 2017

CMOS protection during germanium photodetector processing

IBM1 citations50
US9136303B2Sep 15, 2015

CMOS protection during germanium photodetector processing

IBM1 citations50
US7473636B2Jan 6, 2009

Method to improve time dependent dielectric breakdown

IBM0 citations42

GLOBALFOUNDRIES INC

4 patents

DE SOUZA JOEL P

3 patents

GLOBALFOUNDRIES US INC

3 patents

EDELSTEIN DANIEL C

1 patent

INFINEON TECHNOLOGIES AG

1 patent

SHIU KUEN-TING

1 patent

FOMPEYRINE JEAN

1 patent

SOSA CORTES NORMA E

1 patent