Inventor

RADENS CARL J

US246 patents

⚠️ This page may combine multiple inventors who share the name “RADENS CARL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RADENS CARL J

IBM

High performance FET with elevated source/drain region

Self-trimming method on looped patterns

Silicon-on-insulator vertical array device trench capacitor DRAM

Method for hybrid DRAM cell utilizing confined strap isolation

Trench optical device

Structure and method for MOSFET with metallic gate electrode

Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof

High-density dual-cell flash memory structure

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

Method of making a dual damascene anti-fuse with via before wire

Vertical MOSFET SRAM cell

MOS antifuse with low post-program resistance

MOS transistor

Three-dimensional island pixel photo-sensor

Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch

Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex

Vertical MOSFET

Single sided buried strap

Design layout for a dense memory cell structure

Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch

MOS transistors structure for reducing the size of pitch limited circuits

Shallow trench isolation method utilizing combination of spacer and fill

MOSFET structure and process for low gate induced drain leakage (GILD)

End-point detection

On-chip power supply regulator and temperature control system

Micro-cavity MEMS device and method of fabricating same

Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric

Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

Dual port gain cell with side and top gated read transistor

Dual port gain cell with side and top gated read transistor

SOI device with different crystallographic orientations

Out of the box vertical transistor for eDRAM on SOI

Three-dimensional island pixel photo-sensor

Out of the box vertical transistor for eDRAM on SOI

Method to fabricate passive components using conductive polymer

Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby

Damascene method for improved MOS transistor

Memory cell with vertical transistor and trench capacitor with reduced burried strap

Twin-cell flash memory structure and method

Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation

Inverse T-gate structure using damascene processing

Method for delineation of eDRAM support device notched gate

Structure and method for a compact trench-capacitor DRAM cell with body contact

6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI

High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits

INFINEON TECHNOLOGIES CORP

Single sided buried strap

Semiconductor structure and manufacturing methods

INFINEON TECHNOLOGIES AG

Compact trench capacitor memory cell with body contact

GLOBALFOUNDRIES INC

Method of forming self-aligned metal lines and vias

SIEMENS AG

Tapered electrode for stacked capacitors