Inventor

TOYONAGA MASAHIKO

JP26 patents

⚠️ This page may combine multiple inventors who share the name “TOYONAGA MASAHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOYONAGA MASAHIKO

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones

Method for designing semiconductor integrated circuit

Channel routing method

Placement optimization system aided by cad

Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device

Method for optimizing component placement in designing a semiconductor device by using a cost value

LSI layout design method capable of satisfying timing requirements in a reduced design processing time

Logic synthesis method and logic synthesis apparatus

Method for VLSI layout pattern compaction by using direct access memory

Method for automating top-down design processing for the design of LSI functions and LSI mask layouts

Clock distribution circuit with clock branch circuits connected to outgoing and return lines and outputting synchronized clock signals by summing time integrals of clock signals on the outgoing and return lines

Semiconductor integrated circuit and manufacturing method therefor, semiconductor macro cell and automatic layout method therefor, and mask processing method

Semiconductor integrated circuit capable of compensating for flucuations in power supply voltage level and method of manufacturing the same

LSI wire length estimation and area estimation

System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function

Automatic synthesizing method for logic circuits

Method and apparatus for automatically arranging circuit elements in data-path circuit

Method and apparatus for classifying and evaluating logic circuit

Method of optimizing placement of elements

Delay analysis method and design assist apparatus of semiconductor circuit

LSI design system

High level synthesis method for semiconductor integrated circuit

System and method for sorting count information by summing frequencies of usage and using the sums to determine write addresses

LSI design system

Delay analysis method and design assist apparatus of semiconductor circuit

(unassigned)

Clock circuit and method of designing the same