Inventor

GASKINS DARIUS D

US90 patents

⚠️ This page may combine multiple inventors who share the name “GASKINS DARIUS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GASKINS DARIUS D

DELL USA LP

Dual path memory retrieval system for an interleaved dynamic RAM memory unit

Cache-based computer system employing memory control circuit and method for write allocation and data prefetch

Redundant memory channel array configuration with data striping and error correction capabilities

Integrated delay line

Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order

Interface circuit having zero latency buffer memory and cache memory information transfer

Combined multiprocessor interrupt controller and interprocessor communication mechanism

Apparatus and method for optimal error correcting code to parity conversion

Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency

Multi-purpose usage of transaction backoff and bus architecture supporting same

Cache-based computer system employing a snoop control circuit with write-back suppression

Method and apparatus for eliminating bus contention among multiple drivers without performance degradation

System and method for memory mapping

Store queue including a byte order tracking mechanism for maintaining data coherency

System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus

Method and apparatus for synchronous bus interface optimization

Apparatus and method for optimal error correcting code to parity conversion

Apparatus for queing and storing data writes into valid word patterns

VIA TECH INC

Flexible width data protocol

Sense mechanism for microprocessor bus inversion

Microprocessor with improved thermal monitoring and protection mechanism

Microprocessor with improved performance during P-state transitions

Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature

Apparatus and method for enabling a multi-processor environment on a bus

Frequency-voltage mechanism for microprocessor power management

Microprocessor with selective substrate biasing for clock-gated functional blocks

Method and apparatus for microprocessor temperature control

Apparatus and method for generating a clock signal with reduced jitter

Power state synchronization in a multi-core processor

IP FIRST LLC

Translation lookaside buffer that caches memory type information

Byte-wise tracking on write allocate

Microprocessor having fuse control and selection of clock multiplier

Integrated circuit timing debug apparatus and method

Apparatus and method for improved non-page fault loads and stores

Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor

Method for transferring burst data in a microprocessor

HENRY G GLENN

Power state synchronization in a multi-core processor

Multicore processor power credit management to allow all processing cores to operate at elevated frequency

Detection of uncorrectable re-grown fuses in a microprocessor

Microprocessor with multicore processor power credit management feature

Master core discovering enabled cores in microprocessor comprising plural multi-core dies

Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption

GASKINS DARIUS D

Microprocessor that performs adaptive power throttling

Configurable bus termination for multi-core/multi-package processor configurations

Microprocessor with improved thermal monitoring and protection mechanism

Multi-core microprocessor internal bypass bus

Apparatus and method for delayed synchronous data reception

I P FIRST LLC

Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor

Byte-wise write allocate with retry tracking

DELLUSA L P

Ternary storage dynamic RAM