Inventor
STEPHENS GEOFFREY B
22 patents
Patents
22 patentsUS6031394AFeb 29, 2000
Low voltage CMOS circuit for on/off chip drive at high voltage
IBM67 citations96
US4201800AMay 6, 1980
Hardened photoresist master image mask process
IBM123 citations95
US6275094B1Aug 14, 2001
CMOS device and circuit and method of operation dynamically controlling threshold voltage
IBM40 citations92
US4404577ASep 13, 1983
Electrically alterable read only memory cell
IBM29 citations92
US4172004AOct 23, 1979
Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
IBM35 citations91
US5453705ASep 26, 1995
Reduced power VLSI chip and driver circuit
IBM21 citations89
US5424659AJun 13, 1995
Mixed voltage output buffer circuit
IBM31 citations89
US4481566ANov 6, 1984
On chip charge trap compensated high voltage converter
IBM20 citations82
US4314267AFeb 2, 1982
Dense high performance JFET compatible with NPN transistor formation and merged BIFET
IBM25 citations82
US4357178ANov 2, 1982
Schottky barrier diode with controlled characteristics and fabrication method
IBM26 citations81
US4289834ASep 15, 1981
Dense dry etched multi-level metallurgy with non-overlapped vias
IBM27 citations81
US4412376ANov 1, 1983
Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
IBM25 citations78
US4458407AJul 10, 1984
Process for fabricating semi-conductive oxide between two poly silicon gate electrodes
IBM20 citations76
US4429237AJan 31, 1984
High voltage on chip FET driver
IBM9 citations74
US4395812AAug 2, 1983
Forming an integrated circuit
IBM12 citations73
US4229753AOct 21, 1980
Voltage compensation of temperature coefficient of resistance in an integrated circuit resistor
IBM17 citations73
US4157268AJun 5, 1979
Localized oxidation enhancement for an integrated injection logic circuit
IBM13 citations73
US4373166AFeb 8, 1983
Schottky Barrier diode with controlled characteristics
IBM15 citations68
US4656729AApr 14, 1987
Dual electron injection structure and process with self-limiting oxidation barrier
IBM11 citations66
US5939897AAug 17, 1999
Method and apparatus for testing quiescent current in integrated circuits
IBM5 citations59
US5760598AJun 2, 1998
Method and apparatus for testing quiescent current in integrated circuits
IBM3 citations59
US4326212AApr 20, 1982
Structure and process for optimizing the characteristics of I2 L devices
IBM5 citations57