Inventor
DESHPANDE SANJAY RAGHUNATH
US19 patents
Patents
19 patentsUS6317811B1Nov 13, 2001
Method and system for reissuing load requests in a multi-stream prefetch design
IBM95 citations98
US6606676B1Aug 12, 2003
Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
IBM105 citations97
US6779036B1Aug 17, 2004
Method and apparatus for achieving correct order among bus memory transactions in a physically distributed SMP system
IBM60 citations96
US6725307B1Apr 20, 2004
Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
IBM59 citations94
US6467012B1Oct 15, 2002
Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors
IBM59 citations93
US6516379B1Feb 4, 2003
Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system
IBM38 citations92
US6484220B1Nov 19, 2002
Transfer of data between processors in a multi-processor system
IBM42 citations92
US6449698B1Sep 10, 2002
Method and system for bypass prefetch data path
IBM39 citations92
US6434638B1Aug 13, 2002
Arbitration protocol for peer-to-peer communication in synchronous systems
IBM28 citations92
US5781757AJul 14, 1998
Adaptive scalable cache coherence network for a multiprocessor data processing system
IBM55 citations92
US5717853AFeb 10, 1998
Information handling system having router including first mode for configuring itself, second mode for configuring its connected devices and third mode for system operation
IBM27 citations92
US5673413ASep 30, 1997
Method and apparatus for coherency reporting in a multiprocessing system
IBM43 citations92
US6442597B1Aug 27, 2002
Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory
IBM33 citations91
US6591348B1Jul 8, 2003
Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system
IBM42 citations87
US5692135ANov 25, 1997
Method and system for performing an asymmetric bus arbitration protocol within a data processing system
IBM41 citations87
US5802377ASep 1, 1998
Method and apparatus for implementing multiple interrupt controllers in a multi-processor computer system
IBM8 citations74
US5764998AJun 9, 1998
Method and system for implementing a distributed interrupt controller
IBM8 citations74
US6587930B1Jul 1, 2003
Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
IBM8 citations72
US7529799B2May 5, 2009
Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
IBM2 citations62