Inventor

LIN XI-WEI

US75 patents

⚠️ This page may combine multiple inventors who share the name “LIN XI-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN XI-WEI

VLSI TECHNOLOGY INC

Low power programmable fuse structures

Low power programmable fuse structures and methods for making the same

Method of removing an inorganic antireflective coating from a semiconductor substrate

Metallization technique for gate electrodes and local interconnects

Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device

Via formation using oxide reduction of underlying copper

Selective exclusion of silicide formation to make polysilicon resistors

Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device

On-chip decoupling capacitor system with parallel fuse

Self-aligned processing of semiconductor device features

Method of forming a via hole structure including CVD tungsten silicide barrier layer

Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device

Self-aligned silicidation structure and method of formation thereof

Method of making high resistive structures in salicided process semiconductor devices

Local interconnect formed using silicon spacer

Plasma ash for silicon surface preparation

Method for fabrication of a semiconductor device

Integrated etch process for polysilicon/metal gate

Method of making shallow junction semiconductor devices

Method of improving process robustness of nickel salicide in semiconductors

Reducing the formation of electrical leakage pathways during manufacture of an electronic device

Method for fabrication of a semiconductor device

SYNOPSYS INC

Method and apparatus for generating a layout for a transistor

Filler cells for design optimization in a place-and-route system

Managing integrated circuit stress using dummy diffusion regions

SRAM layouts

Managing integrated circuit stress using dummy diffusion regions

Method and apparatus for placing an integrated circuit device within an integrated circuit layout

Minimizing effects of interconnect variations in integrated circuit designs

Stress-managed revision of integrated circuit layouts

Method of correlating silicon stress to device instance parameters for circuit simulation

Methods for fabricating high-density integrated circuit devices

Minimizing effects of interconnect variations in integrated circuit designs

Managing integrated circuit stress using stress adjustment trenches

Pre-silicon design rule evaluation

Chip cross-section identification and rendering during failure analysis

Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network

Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)

SRAM layouts

Increasing Ion/Ioff ratio in FinFETs and nano-wires

Increasing ION /IOFF ratio in FinFETs and nano-wires

Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network

MOROZ VICTOR

Stress-managed revision of integrated circuit layouts

Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance

Boosting transistor performance with non-rectangular channels

KONINKL PHILIPS ELECTRONICS NV

Self-aligned etch-stop layer formation for semiconductor devices

Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths

LIN XI-WEI

Method of correlating silicon stress to device instance parameters for circuit simulation

Filler cells for design optimization in a place-and-route system

PHILIPS SEMICONDUCTORS INC

Semiconductor arrangement having capacitive structure and manufacture thereof