Inventor

CHAMBERS PETER

US57 patents

⚠️ This page may combine multiple inventors who share the name “CHAMBERS PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAMBERS PETER

VLSI TECHNOLOGY INC

Multi-master PCI bus system within a single integrated circuit

Real time event determination in a universal serial bus system

Virtual contiguous FIFO having the provision of packet-driven automatic endian conversion

Predictive arbitration system for PCI bus agents

System and method to test internal PCI agents

Register-based programmable post-silicon system to patch and dynamically modify the behavior of synchronous state machines

Method and system for hot docking a portable computer to a docking station via the primary PCI bus

Optimizing the performance of asynchronous bus bridges with dynamic transactions

Optimizing peripheral component interconnect transactions in a mixed 32/64-bit environment by eliminating unnecessary data transfers

Virtual contiguous FIFO for combining multiple data packets into a single contiguous stream

Method and system for accurate temporal determination of real-time events within a universal serial bus system

System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller

Smart retry mechanism to program the retry latency of a PCI initiator agent

System using descriptor and having hardware state machine coupled to DMA for implementing peripheral device bus mastering via USB controller or IrDA controller

Mailbox traffic controller

System using DMA and descriptor for implementing peripheral device bus mastering via a universal serial bus controller or an infrared data association controller

Method and system for accurate temporal determination of real-time events within a universal serial bus system

Cache based scan matrix keyboard controller

Reprogrammable state machine and method therefor

Adaptive arbitration mechanism for a shared multi-master bus

Patch mechanism for allowing dynamic modifications of the behavior of a state machine

Method and system for optimized data transfers in a mixed 64-bit/32-bit PCI environment

Memory mapping method for eliminating dual address cycles in a peripheral component interconnect environment

Method for eliminating dual address cycles in a peripheral component interconnect environment

Detection of objects on a computer display

Color signature detection of objects on a computer display

System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status

Multiple entry wavetable address cache to reduce accesses over a PCI bus

Wavetable address cache to reduce accesses over a PCI bus

Method and system for an extensible on silicon bus supporting multiple functional blocks

Multiple bus agent integrated circuit device for connecting to an external bus

Smart target mechanism for eliminating dual address cycles in a peripheral component interconnect environment

System for implementing peripheral device bus mastering in mobile computer via micro-controller for programming DMA controller, generating and sending command signals, and receiving completion status

MICREL INC

Programming and control of an integrated circuit using an externally connected resistor network

Device and method for improved serial bus transaction using incremental address decode

Adaptive decoder for decoding an asynchronous data stream

Input/output circuit for handling unconnected I/O pads

Power saving method in an integrated circuit programming and control circuit

Analog control of a digital decision process

Laser turn-on accelerator independent of bias control loop bandwidth

Numerical value conversion using a look-up table for coefficient storage

Laser turn-on accelerator independent of bias control loop bandwidth

Laser controller integrated circuit including variable resolution data processing device

Minimization of overhead of non-volatile memory operation

Robust power-on meter and method

Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands

KONINKL PHILIPS ELECTRONICS NV

System to detect a power management system resume event from a stylus and touch screen

System and method to test internal PCI agents

STRATOS LIGHTWARE INC

Automatic control of laser diode current and optical power output

VLSI TECHNLOGY INC

Fast response system implementing a sampling clock for extracting stable clock information from a serial data stream with defined jitter characeristics and method therefor