Inventor
WU YOUFENG
US110 patents
⚠️ This page may combine multiple inventors who share the name “WU YOUFENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
36 patentsUS8001421B2Aug 16, 2011
Compiler technique for efficient register checkpointing to support transaction roll-back
INTEL CORP73 citations98
US7032217B2Apr 18, 2006
Method and system for collaborative profiling for continuous detection of profile phase transitions
INTEL CORP84 citations98
US6668372B1Dec 23, 2003
Software profiling method and apparatus
INTEL CORP111 citations98
US6848100B1Jan 25, 2005
Hierarchical software path profiling
INTEL CORP82 citations95
US6202204B1Mar 13, 2001
Comprehensive redundant load elimination for architectures supporting control and data speculation
INTEL CORP66 citations95
US7451121B2Nov 11, 2008
Genetic algorithm for microcode compression
INTEL CORP19 citations93
US7100155B1Aug 29, 2006
Software set-value profiling and code reuse
INTEL CORP20 citations93
US6959435B2Oct 25, 2005
Compiler-directed speculative approach to resolve performance-degrading long latency events in an application
INTEL CORP25 citations93
US6629314B1Sep 30, 2003
Management of reuse invalidation buffer for computation reuse
INTEL CORP20 citations93
US6332214B1Dec 18, 2001
Accurate invalidation profiling for cost effective data speculation
INTEL CORP50 citations93
US6230317B1May 8, 2001
Method and apparatus for software pipelining of nested loops
INTEL CORP38 citations93
US9146844B2Sep 29, 2015
Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region
INTEL CORP17 citations92
US7703088B2Apr 20, 2010
Compressing “warm” code in a dynamic binary translation environment
INTEL CORP21 citations92
US7506217B2Mar 17, 2009
Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability
INTEL CORP28 citations92
US7188234B2Mar 6, 2007
Run-ahead program execution with value prediction
INTEL CORP30 citations92
US7095342B1Aug 22, 2006
Compressing microcode
INTEL CORP19 citations92
US6836841B1Dec 28, 2004
Predicting output of a reuse region using prior execution results associated with the reuse region
INTEL CORP21 citations92
US6571385B1May 27, 2003
Early exit transformations for software pipelining
INTEL CORP41 citations92
US7757221B2Jul 13, 2010
Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints
INTEL CORP28 citations91
US7467377B2Dec 16, 2008
Methods and apparatus for compiler managed first cache bypassing
INTEL CORP22 citations91
US7039909B2May 2, 2006
Method and apparatus for performing compiler transformation of software code using fastforward regions and value specialization
INTEL CORP32 citations91
US6964043B2Nov 8, 2005
Method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code
INTEL CORP45 citations91
US6625725B1Sep 23, 2003
Speculative reuse of code regions
INTEL CORP29 citations91
US7620781B2Nov 17, 2009
Efficient Bloom filter
INTEL CORP23 citations89
US7752613B2Jul 6, 2010
Disambiguation in dynamic binary translation
INTEL CORP22 citations86
US9817644B2Nov 14, 2017
Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region
INTEL CORP5 citations84
US9501135B2Nov 22, 2016
Dynamic core selection for heterogeneous multi-core systems
INTEL CORP6 citations84
US9239712B2Jan 19, 2016
Software pipelining at runtime
INTEL CORP7 citations84
US9170792B2Oct 27, 2015
Dynamic optimization of pipelined software
INTEL CORP8 citations84
US7865885B2Jan 4, 2011
Using transactional memory for precise exception handling in aggressive dynamic binary optimizations
INTEL CORP18 citations84
US7844946B2Nov 30, 2010
Methods and apparatus to form a transactional objective instruction construct from lock-based critical sections
INTEL CORP9 citations84
US7802136B2Sep 21, 2010
Compiler technique for efficient register checkpointing to support transaction roll-back
INTEL CORP11 citations84
US7725887B2May 25, 2010
Method and system for reducing program code size
INTEL CORP8 citations84
US7448031B2Nov 4, 2008
Methods and apparatus to compile a software program to manage parallel μcaches
INTEL CORP10 citations84
US7428731B2Sep 23, 2008
Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators
INTEL CORP15 citations84
US7694281B2Apr 6, 2010
Two-pass MRET trace selection for dynamic optimization
INTEL CORP10 citations83
WANG CHENG
4 patentsUS9152417B2Oct 6, 2015
Expediting execution time memory aliasing checking
WANG CHENG9 citations84
US8132158B2Mar 6, 2012
Mechanism for software transactional memory commit/abort in unmanaged runtime environment
WANG CHENG14 citations84
US8060482B2Nov 15, 2011
Efficient and consistent software transactional memory
WANG CHENG9 citations84
US8522223B2Aug 27, 2013
Automatic function call in multithreaded application
WANG CHENG8 citations83
WU YOUFENG
2 patentsLIU WEI
2 patentsSEQUENT COMPUTER SYSTEMS INC
1 patentKIM HO-SEOP
1 patentBRETERNITZ JR MAURICIO
1 patentCHUNG JAEWOONG
1 patentZHAO CHENGYAN
1 patentSAGER DAVID J
1 patentShowing the top 50 of 110 patents by PatentIndex Score.