Inventor

CRONIN JOHN E

US113 patents

⚠️ This page may combine multiple inventors who share the name “CRONIN JOHN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRONIN JOHN E

IBM

Microconnectors

Reducing pitch with continuously adjustable line and space dimensions

Method and workpiece for connecting a thin layer to a monolithic electronic module&#39;s surface and associated module packaging

Electronic modules with interconnected surface metallization layers and fabrication methods therefore

Cooling microfan arrangements and process

Stacked chip process carrier

Method of making shadow RAM cell having a shallow trench EEPROM

Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit

CMP polishing pad backside modifications for advantageous polishing results

Method for stacked three dimensional device manufacture

Endpoint detection apparatus and method for chemical/mechanical polishing

Shadow ram cell having a shallow trench eeprom

Plural level chip masking

Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias

Cube wireability enhancement with chip-to-chip alignment and thickness control

Electronic modules with interconnected surface metallization layers

Planarized semiconductor structure using subminimum features

Fabrication methods for bidirectional field emission devices and storage structures

Laternal field emmission devices and methods of fabrication

Cooling microfan arrangements and process

Method for planarizing semiconductor structure using subminimum features

Lateral field emission devices

Passivation of metal in metal/polyimide structure

Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions

Etching metal films with complexing chloride plasma

VLSI coaxial wiring structure

Method of forming metal-strapped polysilicon gate electrode for FET device

Method of forming borderless contacts using a removable mandrel

Method of fabricating a stacked via in copper/polyimide beol

High performance direct coupled FET memory cell

Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level

Planarized semiconductor structure with subminimum features

Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal

Method of making overpass mask/insulator for local interconnects

Triple self-aligned metallurgy for semiconductor devices

Stud formation method optimizing insulator gap-fill and metal hole-fill

Method and apparatus for removing heat from a semiconductor device

Multichip module

Process for aligning etch masks on an integrated circuit surface using electromagnetic energy

Variable travel carrier device and method for planarizing semiconductor wafers

Gray level mask

Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions

Method of making a gray level mask

PROSPORTS TECH LLC

Automated clip creation

Interactive seat beacon with customization

Whistle play stopper

E INK CORP

Electro-optic displays, and methods for driving same

ARMSTRONG WORLD IND INC

Ceiling tile transmitter and receiver system

GRANDIOS TECHNOLOGIES LLC

Automatic personal assistance between users devices

PROSPORTS TECHNOLOGIES LLC

Smart field goal detector

Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging