Inventor

MERRITT TODD A

US149 patents

⚠️ This page may combine multiple inventors who share the name “MERRITT TODD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MERRITT TODD A

MICRON TECHNOLOGY INC

Data amplifier having reduced data lines and/or higher data rates

Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Distributed write data drivers for burst access memories

Method for switching between modes of operation

Method for reliably shutting off oscillator pulses to a charge-pump

Method and apparatus for storage of test results within an integrated circuit

Distributed write data drivers for burst access memories

Method and apparatus for storage of test results within an integrated circuit

Layout for a semiconductor memory device having redundant elements

High output high efficiency low voltage charge pump

Distributed write data drivers for burst access memories

Method and apparatus for testing an embedded DRAM

Distributed write data drivers for burst access memories

Die architecture accommodating high-speed semiconductor devices

Method for storing information in a semiconductor device

Read only memory embedded in a dynamic random access memory

Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Layout for semiconductor memory device wherein intercoupling lines are shared by two sets of fuse banks and two sets of redundant elements not simultaneously active

Die architecture accommodating high-speed semiconductor devices

Die architecture accommodating high-speed semiconductor devices

Structure and a method for storing information in a semiconductor device

Architecture and package orientation for high speed memory devices

Layout for a semiconductor memory device having redundant elements

Low power, high speed level shifter

Distributed write data drivers for burst access memories

Method and structures for reduced parasitic capacitance in integrated circuit metallizations

Distributed write data drivers for burst access memories

Distributed write data drivers for burst access memories

Method and structures for reduced parasitic capacitance in integrated circuit metallizations

Distributed write data drivers for burst access memories

Layout for semiconductor memory device having a plurality of rows and columns of circuit cells divided into first and second planes that are not simultaneously active

Multiplexed data transfer arrangement including a multi-phase signal generator for latency control

Memory device having data path containing dual mode flip-flop used for normal operation and for internal testing

Low power, high speed level shifter

Method and apparatus for translating signals

Memory device with command buffer

Die architecture accommodating high-speed semiconductor devices

Apparatus for testing redundant elements in a packaged semiconductor memory device

Integrated circuit clock input buffer

Multi-bank architecture for a wide I/O DRAM

Method and circuit for sending a signal in a semiconductor device during a setup time

Method and apparatus for translating signals

Methods using a data read latch circuit in a semiconductor device

Circuit and method for varying a period of an internal control signal during a test mode

Method and apparatus using a data read latch circuit in a semiconductor device

Method and circuit for self-latching data read lines in the data output path of a semiconductor memory device

MICRON SEMICONDUCTOR INC

Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal

Memory device with pulse circuit for timing data output, and method for outputting data

MICRON TECHNLOGY INC

Multiplexed semiconductor data transfer arrangement with timing signal generator

WALKER ROBERT M

Memory having internal processors and data communication methods in memory