Inventor

HSIEH CHIA-TA

TW152 patents

⚠️ This page may combine multiple inventors who share the name “HSIEH CHIA-TA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSIEH CHIA-TA

TAIWAN SEMICONDUCTOR MFG

Storage nitride encapsulation for non-planar sonos NAND flash charge retention

Split-gate flash with source/drain multi-sharing

Method to increase coupling ratio of source to floating gate in split-gate flash

Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate

Method to increase coupling ratio of source to floating gate in split-gate flash

Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash

Poly tip formation and self-align source process for split-gate flash cell

Method to fabricate a new structure with multi-self-aligned for split-gate flash

Flash EEPROM with function bit by bit erasing

Flash with finger-like floating gate

Stacked-gate flash memory cell with folding gate and increased coupling ratio

Method of manufacturing a flash memory cell with high programming efficiency by coupling from floating gate to sidewall

Flash EEPROM with function bit by bit erasing

Method to fabricate a square poly spacer in flash

Method to improve the coupling ratio of top gate to floating gate in flash

Method for forming split-gate flash cell for salicide and self-align contact

Split-gate flash memory device having floating gate electrode with sharp peak

Split gate flash cell for multiple storage

Poly tip formation and self-align source process for split-gate flash cell

Method to increase coupling ratio of source to floating gate in split-gate flash

Method of forming split-gate flash cell for salicide and self-align contact

Split-gate flash cell for virtual ground architecture

Method of forming poly tip to improve erasing and programming speed split gate flash

Forming self-align source line for memory array

Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash

Method to fabricate poly tip in split-gate flash

Method for forming mirror image split gate flash memory devices by forming a central source line slot

Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak

Process of forming an EEPROM device having a split gate

Source side injection programming and tip erasing P-channel split gate flash memory cell

Vertical channels in split-gate flash memory cell

Program and erase method for a split gate flash EEPROM

Two mask method for reducing field oxide encroachment in memory arrays

Method of forming isolation by nitrogen implant to reduce bird&#39;s beak

Method for forming vertical channels in split-gate flash memory cell

Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash

Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation

Split-gate flash cell

Method of forming a floating gate self-aligned to STI on EEPROM

Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation

Structure with protruding source in split-gate flash

Split-gate flash cell

Method to free control tunneling oxide thickness on poly tip of flash

Split gate flash with step poly to improve program speed

Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio

Method to fabricate sharp tip of poly in split gate flash

Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash

Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash

Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM

HUNG CHIH-WEI

Non-volatile field programmable gate array

Method of forming isolation by nitrogen implant to reduce bird's beak