Inventor

DABRAL SANJAY

US129 patents

⚠️ This page may combine multiple inventors who share the name “DABRAL SANJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DABRAL SANJAY

INTEL CORP

Apparatus for interconnecting multiple devices on a circuit board

Link power saving state

Computer system with a semi-differential bus signaling scheme

Dynamically modulating link width

Method and apparatus for interconnecting multiple devices on a circuit board

Method and apparatus for configuring the pinout of an integrated circuit

Flexible cable for high-speed interconnect

Enhanced conductivity body biased PMOS driver

System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof

Enhanced conductivity body biased PMOS driver

Orienting multiple processors on two sides of a printed circuit board

Charge sharing and charge recycling for an on-chip bus

Method and apparatus for generating a reference voltage signal derived from complementary signals

Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances

Compensating a characteristic of a circuit

Methods and apparatuses to effect a variable-width link

Link power saving state

Method and apparatus for periodically retraining a serial links interface

Predriver logic circuit

Low gain phase-locked loop circuit

Low gain phase-locked loop circuit

Reference voltage distribution for multiload i/o systems

Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link

Method and apparatus for acknowledgement-based handshake mechanism for interactively training links

Method, system, and apparatus for loopback entry and exit

Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection

Cache based physical layer self test

Diode and transistor design for high speed I/O

Low cost and high speed 3-load printed wiring board bus topology

Technique to create link determinism

Testing for digital signaling

Programmable passive equalizer

Pre-drivers for current-mode I/O drivers

Fast bi-directional tristateable line driver

APPLE INC

Systems and methods for forming die sets with die-to-die routing and metallic seals

Systems and methods for implementing a scalable system

Systems and methods for implementing a scalable system

Interconnecting dies by stitch routing

Die stitching and harvesting of arrayed structures

Die-to-die routing through a seal ring

High density 3D interconnect configuration

Power management system switched capacitor voltage regulator with integrated passive device

EDRAM/DRAM fabricated capacitors for use in on-chip PMUS and as decoupling capacitors in an integrated EDRAM/DRAM and PMU system

Reference clock sharing

RAINBOW DISPLAYS INC

Assembling and sealing large, hermetic and semi-hermetic, h-tiled, flat-paneled displays

Assembling and sealing large, hermetic and semi-hermetic H-tile flat panel display

PLANAR LABS CORP

Method and apparatus for electrodialytic chemical mechanical polishing and deposition

(unassigned)

Apparatus and methods for multi-lingual user access

YEUNG EVELINA F

Programmable passive equalizer

CHERUKURI NAVEEN

Link power savings with state retention