Inventor

KUO DI-SON

TW109 patents

⚠️ This page may combine multiple inventors who share the name “KUO DI-SON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO DI-SON

TAIWAN SEMICONDUCTOR MFG

Test structures for monitoring gate oxide defect densities and the plasma antenna effect

Multi-level, split-gate, flash memory cell and method of manufacture thereof

Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions

Multi-level, split-gate, flash memory cell

Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory

Method of making embedded flash memory with salicide and sac structure

Multi-level split- gate flash memory cell

Method to increase coupling ratio of source to floating gate in split-gate flash

Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate

Method to increase coupling ratio of source to floating gate in split-gate flash

Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash

Poly tip formation and self-align source process for split-gate flash cell

Stack gate flash memory cell featuring symmetric self aligned contact structures

Method to fabricate a new structure with multi-self-aligned for split-gate flash

Stacked-gate flash memory cell with folding gate and increased coupling ratio

Method for forming split-gate flash cell for salicide and self-align contact

Split-gate flash memory device having floating gate electrode with sharp peak

Flash memory cell with vertically oriented channel

Split gate flash cell for multiple storage

Method of manufacture of vertical split gate flash memory device

Poly tip formation and self-align source process for split-gate flash cell

Method to increase coupling ratio of source to floating gate in split-gate flash

Method of forming split-gate flash cell for salicide and self-align contact

Implant method to improve characteristics of high voltage isolation and high voltage breakdown

Split-gate flash cell for virtual ground architecture

Test structures for monitoring gate oxide defect densities and the plasma antenna effect

Method of forming poly tip to improve erasing and programming speed split gate flash

Forming self-align source line for memory array

Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash

Method to fabricate poly tip in split-gate flash

Method for forming mirror image split gate flash memory devices by forming a central source line slot

Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process

Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak

Method for forming vertical channel flash memory cell using P/N junction isolation

Process of forming an EEPROM device having a split gate

Source side injection programming and tip erasing P-channel split gate flash memory cell

Method of manufacture of vertical split gate flash memory device

Vertical channels in split-gate flash memory cell

Flash memory cell with vertical channels, and source/drain bus lines

Program and erase method for a split gate flash EEPROM

Process for forming self-aligned source in flash cell using SiN spacer as hard mask

Two mask method for reducing field oxide encroachment in memory arrays

Method for forming vertical channels in split-gate flash memory cell

Method for forming vertical channel flash memory cell and device manufactured thereby

Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash

Split-gate flash cell

Method of forming a floating gate self-aligned to STI on EEPROM

(unassigned)

Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices

PHILIPS ELECTRONICS NA

Electrically erasable and programmable read only memory with non-uniform dielectric thickness

PHILIPS CORP

Electrically erasable and programmable read only memory with trench structure