Inventor
LEDDIGE MICHAEL W
US30 patents
⚠️ This page may combine multiple inventors who share the name “LEDDIGE MICHAEL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS6144576ANov 7, 2000
Method and apparatus for implementing a serial memory architecture
INTEL CORP277 citations99
US6587912B2Jul 1, 2003
Method and apparatus for implementing multiple memory buses on a memory module
INTEL CORP407 citations98
US6477614B1Nov 5, 2002
Method for implementing multiple memory buses on a memory module
INTEL CORP308 citations98
US6005776ADec 21, 1999
Vertical connector based packaging solution for integrated circuits
INTEL CORP102 citations98
US6353539B1Mar 5, 2002
Method and apparatus for matched length routing of back-to-back package placement
INTEL CORP74 citations96
US7402048B2Jul 22, 2008
Technique for blind-mating daughtercard to mainboard
INTEL CORP68 citations94
US6891899B2May 10, 2005
System and method for bit encoding to increase data transfer rate
INTEL CORP20 citations92
US6788222B2Sep 7, 2004
Low weight data encoding for minimal power delivery impact
INTEL CORP23 citations92
US6366466B1Apr 2, 2002
Multi-layer printed circuit board with signal traces of varying width
INTEL CORP50 citations92
US6362973B1Mar 26, 2002
Multilayer printed circuit board with placebo vias for controlling interconnect skew
INTEL CORP18 citations84
US7194572B2Mar 20, 2007
Memory system and method to reduce reflection and signal degradation
INTEL CORP9 citations74
US7133962B2Nov 7, 2006
Circulator chain memory command and address bus topology
INTEL CORP7 citations74
US6724082B2Apr 20, 2004
Systems having modules with selectable on die terminations
INTEL CORP8 citations74
US6711640B1Mar 23, 2004
Split delay transmission line
INTEL CORP7 citations74
US6708243B1Mar 16, 2004
Computer assembly with stub traces coupled to vias to add capacitance at the vias
INTEL CORP9 citations74
US6686762B2Feb 3, 2004
Memory module using DRAM package to match channel impedance
INTEL CORP8 citations74
US6515555B2Feb 4, 2003
Memory module with parallel stub traces
INTEL CORP8 citations74
US9910814B2Mar 6, 2018
Method, apparatus and system for single-ended communication of transaction layer packets
INTEL CORP2 citations72
US8775991B2Jul 8, 2014
Interchangeable connection arrays for double-sided DIMM placement
INTEL CORP4 citations70
US6918078B2Jul 12, 2005
Systems with modules sharing terminations
INTEL CORP4 citations63
US6631083B2Oct 7, 2003
Systems with modules and clocking therefore
INTEL CORP5 citations63
US6539449B1Mar 25, 2003
Capacitively loaded continuity module
INTEL CORP5 citations63
US10078612B2Sep 18, 2018
Mode selective balanced encoded interconnect
INTEL CORP0 citations49
US9330039B2May 3, 2016
Crosstalk aware encoding for a data bus
INTEL CORP0 citations46
US9632961B2Apr 25, 2017
Crosstalk aware decoding for a data bus
INTEL CORP0 citations45