Inventor

WANG LI-KONG

US77 patents

⚠️ This page may combine multiple inventors who share the name “WANG LI-KONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG LI-KONG

IBM

Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same

Chip packaging system and method using deposited diamond film

Method and structure for providing improved thermal conduction for silicon semiconductor devices

Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate

Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory

Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof

Micromachined electromechanical (MEM) random access memory array and method of making same

Self-refresh on-chip voltage generator

Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby

High performance multi-mesa field effect transistor

Method of fabricating silicon devices on sapphire with wafer bonding at low temperature

Memory array employing single three-terminal non-volatile storage elements

Hierarchical power supply noise monitoring device and system for very large scale integrated circuits

Non-volatile memory using ferroelectric gate field-effect transistors

Three-dimensional island pixel photo-sensor

Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby

Memory system capable of operating at high temperatures and method for fabricating the same

Data retention registers

Restore tracking system for DRAM

Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate

Boosted sensing ground circuit

Method and structure for providing improved thermal conduction for silicon semiconductor devices

Content addressable memory having reduced power consumption

System and method for sequential testing of high speed serial link core

Three-dimensional island pixel photo-sensor

Memory system capable of operating at high temperatures and method for fabricating the same

Method to fabricate passive components using conductive polymer

Self-aligned, planarized thin-film transistors, devices employing the same

Dual gate FET and process

Method for fabricating flash memory device using dual damascene process

Fuse latch array system for an embedded DRAM having a micro-cell architecture

Micro-cell redundancy scheme for high performance eDRAM

Method for fabricating semiconductor devices with different properties using maskless process

Dual gate FET and process

Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components

Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication

Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating

Programmable DC voltage generator system

Hierarchical built-in self-test for system-on-chip design

Low-power static column redundancy scheme for semiconductor memories

Decoding scheme for a stacked bank architecture

Multi-port memory device and system for addressing the multi-port memory device

Chip packaging system and method using deposited diamond film

System and method for preventing noise cross contamination between embedded DRAM and system chip

High performance semiconductor memory device with low power consumption

Refresh control circuit for low-power SRAM applications

Integrated power solution for system on chip applications

Segmented content addressable memory architecture for improved cycle time and reduced power consumption

System level device for battery and integrated circuit integration

BELL TELEPHONE LABOR INC

Process for forming complementary integrated circuit devices