Inventor

LAKHANI VINOD C

US42 patents

⚠️ This page may combine multiple inventors who share the name “LAKHANI VINOD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAKHANI VINOD C

MICRON TECHNOLOGY INC

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system having flexible architecture and method

Memory system having flexible architecture and method

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure

Memory system having flexible bus structure and method

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

System and method for assigning addresses to memory devices

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

Memory system having flexible bus structure and method

Memory system having read modify write function and method

System and method for selecting shorted wordlines of an array having dual wordline drivers

System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers

System and method for assigning addresses to memory devices

Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

Memory system having flexible addressing and method using tag and data bus communication

Apparatus and method for selecting data bits read from a multistate memory

Memory system having flexible addressing and method using tag and data bus communication

Apparatus and method for selecting data bits read from a multistate memory

Segmented non-volatile memory array with multiple sources with improved word line control circuitry

Method for assigning addresses to memory devices

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Method of controlling a memory device by way of a system bus

Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

Memory system having flexible bus structure and method

Memory system having flexible bus structure and method

Memory system having flexible bus structure and method

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system having flexible bus structure and method

Memory system having flexible bus structure and method

Method for assigning addresses to memory devices

MICRON QUANTUM DEVICES INC

Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

Segmented non-volatile memory array with multiple sources with improved word line control circuitry

Apparatus and method for selecting data bits read from a multistate memory

NORMAN ROBERT D

Method for assigning addresses to memory devices