Inventor
YOSHIKAWA STEPHANIE A
US3 patents
Patents
3 patentsUS5933757AAug 3, 1999
Etch process selective to cobalt silicide for formation of integrated circuit structures
LSI LOGIC CORP265 citations97
US5902129AMay 11, 1999
Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers
LSI LOGIC CORP87 citations95
US6054062AApr 25, 2000
Method and apparatus for agitating an etchant
LSI LOGIC CORP17 citations74