Inventor

KOBURGER III CHARLES WILLIAM

US69 patents

⚠️ This page may combine multiple inventors who share the name “KOBURGER III CHARLES WILLIAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOBURGER III CHARLES WILLIAM

IBM

Method for forming quadruple density sidewall image transfer (SIT) structures

Method for manufacturing a multi-level interconnect structure

Integrated circuit chip utilizing carbon nanotube composite interconnection vias

Vertical nanotube semiconductor device structures and methods of forming the same

Micro-electro-mechanical valves and pumps and methods of fabricating same

Memory devices using carbon nanotube (CNT) technologies

Layout and process to contact sub-lithographic structures

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Wrap-around gate field effect transistor

Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes

Strained semiconductor device structures

Moving lens for immersion optical lithography

Selective synthesis of semiconducting carbon nanotubes

Method of forming finFET of variable channel width

Method for making integrated circuit chip having carbon nanotube composite interconnection vias

Dual gated finfet gain cell

Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby

Methods and structures for promoting stable synthesis of carbon nanotubes

Method of forming FinFET gates without long etches

Self-aligned dielectric isolation for FinFET devices

Phase change memory cell with vertical transistor

Vertical carbon nanotube field effect transistors and arrays

Sidewall image transfer processes for forming multiple line-widths

Method of forming a dual gated FinFET gain cell

Methods and semiconductor structures for latch-up suppression using a conductive region

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Method of forming a dual gated FinFET gain cell

Micro-electro-mechanical valves and pumps

Methods and semiconductor structures for latch-up suppression using a conductive region

Shallow trench isolation fill by liquid phase deposition of SiO2

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Methods and semiconductor structures for latch-up suppression using a conductive region

Methods for forming a wrap-around gate field effect transistor

Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers

Integrated circuit chip utilizing oriented carbon nanotube conductive layers

High performance single event upset hardened SRAM cell

Low-leakage borderless contacts to doped regions

Semiconductor transistors with contact holes close to gates

Layout and process to contact sub-lithographic structures

Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby

Non-volatile switching and memory devices using vertical nanotubes

Methods of forming low-k dielectric layers containing carbon nanostructures

Electric fuses using CNTs (carbon nanotubes)

Memory devices using carbon nanotube (CNT) technologies

Well isolation trenches (WIT) for CMOS devices

Methods of forming alternating phase shift masks having improved phase-shift tolerance

Passive electrically testable acceleration and voltage measurement devices

Hybrid substrates and methods for forming such hybrid substrates

Method of fabricating semiconductor structures for latch-up suppression

FURUKAWA TOSHIHARU

Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby