P

Inventor

DAMARAJU SATISH K

US13 patents
⚠️ This page may combine multiple inventors who share the name “DAMARAJU SATISH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

8 patents
US9823719B2Nov 21, 2017

Controlling power delivery to a processor via a bypass

INTEL CORP11 citations92
US10429913B2Oct 1, 2019

Controlling power delivery to a processor via a bypass

INTEL CORP4 citations83
US10409346B2Sep 10, 2019

Controlling power delivery to a processor via a bypass

INTEL CORP4 citations83
US10146283B2Dec 4, 2018

Controlling power delivery to a processor via a bypass

INTEL CORP4 citations83
US11157052B2Oct 26, 2021

Controlling power delivery to a processor via a bypass

INTEL CORP2 citations72
US7155574B2Dec 26, 2006

Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory

INTEL CORP0 citations52
US8345491B2Jan 1, 2013

Memory cell write

INTEL CORP0 citations47
US8050116B2Nov 1, 2011

Memory cell write

INTEL CORP0 citations47

DAMARAJU SATISH K

2 patents
US8448010B2May 21, 2013

Increasing memory bandwidth in processor-based systems

DAMARAJU SATISH K2 citations51
US9336008B2May 10, 2016

Shared function multi-ported ROM apparatus and method

DAMARAJU SATISH K1 citations48

KOKER ALTUG

1 patent
US9075741B2Jul 7, 2015

Dynamic error handling using parity and redundant rows

KOKER ALTUG4 citations72

SODHI INDER M

1 patent
US8713256B2Apr 29, 2014

Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance

SODHI INDER M4 citations72

TAHOE RES LTD

1 patent
US11687135B2Jun 27, 2023

Controlling power delivery to a processor via a bypass

TAHOE RES LTD0 citations62