Inventor

MURTHY ANAND

US128 patents

⚠️ This page may combine multiple inventors who share the name “MURTHY ANAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MURTHY ANAND

INTEL CORP

Strained transistor integration for CMOS

Method for improving transistor performance through reducing the salicide interface resistance

Semiconductor transistor having a stressed channel

Semiconductor transistor having a stressed channel

MOS transistor structure and method of fabrication

Transistor structure and method of fabrication

Semiconductor transistor having a stressed channel

Cobalt salicidation method on a silicon germanium film

Double-gate transistor with enhanced carrier mobility

Polysilicon-germanium MOSFET gate electrodes

CMOS transistor junction regions formed by a CVD etching and deposition sequence

Semiconductor device having deposited silicon regions and a method of fabrication

Method for improving transistor performance through reducing the salicide interface resistance

Transistor gate electrode having conductor material layer

Transistor structure and method of fabrication

Graded high germanium compound films for strained semiconductor devices

Transistor gate electrode having conductor material layer

Semiconductor transistor having a stressed channel

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

MOS transistor structure and method of fabrication

Semiconductor device having self-aligned epitaxial source and drain extensions

Formation of strain-inducing films

CMOS transistor junction regions formed by a CVD etching and deposition sequence

Fabricating strained channel epitaxial source/drain transistors

Fabricating strained channel epitaxial source/drain transistors

Self aligned compact bipolar junction transistor layout and method of making same

Method for fabricating a bipolar transistor base

Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer

Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions

CMOS device and method of manufacturing same

Multi-component strain-inducing semiconductor regions

Selective deposition to improve selectivity and structures formed thereby

Methods for selective deposition to improve selectivity

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs

Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

Transistor gate electrode having conductor material layer

Selective etch for patterning a semiconductor film deposited non-selectively

High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS

Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication

Transistor structure with indium phosphide channel

Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material

CMOS transistor junction regions formed by a CVD etching and deposition sequence

Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain

Bipolar junction transistor with improved extrinsic base region and method of fabrication

Source or drain structures with low resistivity

KIM SEIYON

Nanowire transistor with underlayer etch stops

WEBER CORY

Enhanced dislocation stress transistor