P

Inventor

BOYANOV BOYAN

US84 patents
⚠️ This page may combine multiple inventors who share the name “BOYANOV BOYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

29 patents
US7662689B2Feb 16, 2010

Strained transistor integration for CMOS

INTEL CORP343 citations99
US6949482B2Sep 27, 2005

Method for improving transistor performance through reducing the salicide interface resistance

INTEL CORP100 citations99
US6974733B2Dec 13, 2005

Double-gate transistor with enhanced carrier mobility

INTEL CORP95 citations98
US6812086B2Nov 2, 2004

Method of making a semiconductor transistor

INTEL CORP136 citations98
US7274055B2Sep 25, 2007

Method for improving transistor performance through reducing the salicide interface resistance

INTEL CORP26 citations96
US7223679B2May 29, 2007

Transistor gate electrode having conductor material layer

INTEL CORP34 citations96
US7968957B2Jun 28, 2011

Transistor gate electrode having conductor material layer

INTEL CORP11 citations93
US7303989B2Dec 4, 2007

Using zeolites to improve the mechanical strength of low-k interlayer dielectrics

INTEL CORP22 citations93
US6746967B2Jun 8, 2004

Etching metal using sonication

INTEL CORP47 citations93
US7772702B2Aug 10, 2010

Dielectric spacers for metal interconnects and method to form the same

INTEL CORP25 citations92
US7649239B2Jan 19, 2010

Dielectric spacers for metal interconnects and method to form the same

INTEL CORP22 citations92
US7427775B2Sep 23, 2008

Fabricating strained channel epitaxial source/drain transistors

INTEL CORP17 citations92
US7226842B2Jun 5, 2007

Fabricating strained channel epitaxial source/drain transistors

INTEL CORP27 citations92
US6933589B2Aug 23, 2005

Method of making a semiconductor transistor

INTEL CORP32 citations92
US6723622B2Apr 20, 2004

Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer

INTEL CORP38 citations92
US6703291B1Mar 9, 2004

Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions

INTEL CORP25 citations92
US9754886B2Sep 5, 2017

Semiconductor interconnect structures

INTEL CORP5 citations84
US9627321B2Apr 18, 2017

Methods and apparatuses to form self-aligned caps

INTEL CORP4 citations84
US9112029B2Aug 18, 2015

Strained transistor integration for CMOS

INTEL CORP4 citations84
US7772706B2Aug 10, 2010

Air-gap ILD with unlanded vias

INTEL CORP14 citations84
US7365375B2Apr 29, 2008

Organic-framework zeolite interlayer dielectrics

INTEL CORP10 citations84
US7335586B2Feb 26, 2008

Sealing porous dielectric material using plasma-induced surface polymerization

INTEL CORP12 citations84
US7220668B2May 22, 2007

Method of patterning a porous dielectric material

INTEL CORP11 citations84
US9064872B2Jun 23, 2015

Semiconductor interconnect structures

INTEL CORP8 citations82
US7923760B2Apr 12, 2011

Dielectric spacers for metal interconnects and method to form the same

INTEL CORP5 citations74
US7642610B2Jan 5, 2010

Transistor gate electrode having conductor material layer

INTEL CORP7 citations74
US10446493B2Oct 15, 2019

Methods and apparatuses to form self-aligned caps

INTEL CORP1 citations73
US9455224B2Sep 27, 2016

Semiconductor interconnect structures

INTEL CORP3 citations73
US9437710B2Sep 6, 2016

Method for improving transistor performance through reducing the salicide interface resistance

INTEL CORP2 citations63

ILLUMINA INC

11 patents

ILLUMINA CAMBRIDGE LTD

3 patents

BOYANOV BOYAN

2 patents

ILUMINA INC

2 patents

MURTHY ANAND

2 patents

HUSSEIN MAKAREM A

1 patent

Showing the top 50 of 84 patents by PatentIndex Score.