Inventor
YANG HSU KAI
US30 patents
⚠️ This page may combine multiple inventors who share the name “YANG HSU KAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MAGIC TECHNOLOGIES INC
15 patentsUS7852662B2Dec 14, 2010
Spin-torque MRAM: spin-RAM, array
MAGIC TECHNOLOGIES INC56 citations94
US7782661B2Aug 24, 2010
Boosted gate voltage programming for spin-torque MRAM array
MAGIC TECHNOLOGIES INC26 citations92
US7499314B2Mar 3, 2009
Reference cell scheme for MRAM
MAGIC TECHNOLOGIES INC21 citations92
US8018758B2Sep 13, 2011
Gate drive voltage boost schemes for memory array
MAGIC TECHNOLOGIES INC7 citations84
US7977111B2Jul 12, 2011
Devices using addressable magnetic tunnel junction array to detect magnetic particles
MAGIC TECHNOLOGIES INC7 citations84
US7480172B2Jan 20, 2009
Programming scheme for segmented word line MRAM array
MAGIC TECHNOLOGIES INC15 citations84
US7362644B2Apr 22, 2008
Configurable MRAM and method of configuration
MAGIC TECHNOLOGIES INC17 citations84
US7321507B2Jan 22, 2008
Reference cell scheme for MRAM
MAGIC TECHNOLOGIES INC14 citations84
US7957183B2Jun 7, 2011
Single bit line SMT MRAM array architecture and the programming method
MAGIC TECHNOLOGIES INC2 citations63
US8654577B2Feb 18, 2014
Shared bit line SMT MRAM array with shunting transistors between bit lines
MAGIC TECHNOLOGIES INC2 citations62
US8570793B1Oct 29, 2013
Shared bit line SMT MRAM array with shunting transistors between bit lines
MAGIC TECHNOLOGIES INC3 citations62
US7609543B2Oct 27, 2009
Method and implementation of stress test for MRAM
MAGIC TECHNOLOGIES INC3 citations62
US7986572B2Jul 26, 2011
Magnetic memory capable of minimizing gate voltage stress in unselected memory cells
MAGIC TECHNOLOGIES INC1 citations52
US8576618B2Nov 5, 2013
Shared bit line SMT MRAM array with shunting transistors between bit lines
MAGIC TECHNOLOGIES INC0 citations51
US8565014B2Oct 22, 2013
Shared bit line SMT MRAM array with shunting transistors between bit lines
MAGIC TECHNOLOGIES INC0 citations51
YANG HSU KAI
7 patentsUS9170879B2Oct 27, 2015
Method and apparatus for scrubbing accumulated data errors from a memory system
YANG HSU KAI17 citations83
US8274819B2Sep 25, 2012
Read disturb free SMT MRAM reference cell circuit
YANG HSU KAI7 citations83
US8775865B2Jul 8, 2014
Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits
YANG HSU KAI6 citations72
US12153085B2Nov 26, 2024
Massively independent testers system
YANG HSU KAI0 citations62
US8437181B2May 7, 2013
Shared bit line SMT MRAM array with shunting transistors between the bit lines
YANG HSU KAI1 citations61
US8248841B2Aug 21, 2012
Boosted gate voltage programming for spin-torque MRAM array
YANG HSU KAI1 citations51
US11396106B2Jul 26, 2022
Hair cutting device adapted for cutting one's own hair
YANG HSU KAI0 citations37
APPLIED SPINTRONICS INC
4 patentsUS7184302B2Feb 27, 2007
Highly efficient segmented word line MRAM array
APPLIED SPINTRONICS INC28 citations92
US7085183B2Aug 1, 2006
Adaptive algorithm for MRAM manufacturing
APPLIED SPINTRONICS INC14 citations91
US7224628B2May 29, 2007
Adaptive algorithm for MRAM manufacturing
APPLIED SPINTRONICS INC6 citations72
US7180769B2Feb 20, 2007
World line segment select transistor on word line current source side
APPLIED SPINTRONICS INC2 citations58