Inventor

ZUCHOWSKI PAUL S

US40 patents

⚠️ This page may combine multiple inventors who share the name “ZUCHOWSKI PAUL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZUCHOWSKI PAUL S

IBM

Voltage island chip implementation

Voltage island chip implementation

Voltage island design planning

Method for supply voltage drop analysis during placement phase of chip design

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

Simplified tiling pattern method

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

Method of integrated circuit design by selection of noise tolerant gates

Integrated circuit and method of manufacture for avoiding damage by electrostatic charge

Integrated circuit testing methods using well bias modification

Method of automated design and checking for ESD robustness

Automated fuse blow software system

System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA

Substitution of non-minimum groundrule cells for non-critical minimum groundrule cells to increase yield

Multiple supply gate array backfill structure

System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA

Nested voltage island architecture

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

Integrated circuit testing methods using well bias modification

Method for increasing the manufacturing yield of programmable logic devices

Method and apparatus for manufacturing diamond shaped chips

Structure for an on-demand power supply current modification system for an integrated circuit

Mechanism for detection and compensation of NBTI induced threshold degradation

System architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit

Method and system for extending the useful life of another system

Method and system for extending the useful life of another system

Integrated circuit testing method using well bias modification

Testing using independently controllable voltage islands

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

Method and apparatus for manufacturing diamond shaped chips

Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit

Structure for system for extending the useful life of another system

IC tiling pattern method, IC so formed and analysis method

LACKEY DAVID E

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

INTERNAT BUSINESS MACHINES COM

Integrated circuit testing methods using well bias modification

GLOBALFOUNDRIES INC

Reverse performance binning

BARROWS COREY K

On-demand power supply current modification system and method for an integrated circuit