Inventor
KALAFATIS STAVROS
US13 patents
Patents
13 patentsUS6535905B1Mar 18, 2003
Method and apparatus for thread switching within a multithreaded processor
INTEL CORP180 citations98
US6151671ANov 21, 2000
System and method of maintaining and utilizing multiple return stack buffers
INTEL CORP97 citations96
US6981261B2Dec 27, 2005
Method and apparatus for thread switching within a multithreaded processor
INTEL CORP47 citations95
US6795845B2Sep 21, 2004
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction
INTEL CORP37 citations95
US6785890B2Aug 31, 2004
Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread
INTEL CORP39 citations95
US6055630AApr 25, 2000
System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
INTEL CORP73 citations95
US6374350B1Apr 16, 2002
System and method of maintaining and utilizing multiple return stack buffers
INTEL CORP58 citations94
US6971104B2Nov 29, 2005
Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction
INTEL CORP18 citations92
US6865740B2Mar 8, 2005
Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor
INTEL CORP12 citations92
US6854118B2Feb 8, 2005
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information
INTEL CORP16 citations92
US5546434AAug 13, 1996
Dual edge adjusting digital phase-locked loop having one-half reference clock jitter
INTEL CORP19 citations92
US7448025B2Nov 4, 2008
Qualification of event detection by thread ID and thread privilege level
INTEL CORP35 citations86
US6850961B2Feb 1, 2005
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition
INTEL CORP11 citations81