Inventor

SINHAROY BALARAM

US188 patents

⚠️ This page may combine multiple inventors who share the name “SINHAROY BALARAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINHAROY BALARAM

IBM

Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution

Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor

Performance throttling for temperature reduction in a microprocessor

Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions

Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions

Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint

Method and system for dynamically shared completion table supporting multiple threads in a processing system

Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches

Information handling system with real and virtual load/store instruction issue queue

Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture

Specialized memory move barrier operations

Handling of address conflicts during asynchronous memory move operations

Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes

Branch prediction circuits and methods and systems using the same

Use of software hint for branch prediction in the absence of hint bit in the branch instruction

Apparatus and method for recovering a link stack from mis-speculation

Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program

Apparatus and method for performing branch predictions using dual branch history tables and for updating such branch history tables

Prefetching instructions in mis-predicted path for low confidence branches

Global history vector recovery circuits and methods and systems using the same

Increasing the overall prediction accuracy for multi-cycle branch prediction and apparatus by enabling quick recovery

Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements

Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor

Mechanism to save and restore cache and translation trace for fast context switch

Enabling and disabling cache bypass using predicted cache line usage

Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Method and system for software control of hardware branch prediction mechanism in a data processor

Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache

Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor

Method and apparatus for selecting an instruction thread for processing in a multi-thread processor

Software hint to improve the branch target prediction accuracy

Data processing system, processor and method of data processing having improved branch target address cache

Enhanced STCX design to improve subsequent load efficiency

Localized cache block flush instruction

Address translation for sending real address to memory subsystem in effective address based load-store unit

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Address translation for sending real address to memory subsystem in effective address based load-store unit

Completion arbitration for more than two threads based on resource limitations

Reporting of partially performed memory move

Completion of asynchronous memory move in the presence of a barrier operation

ARIMILLI RAVI K

Fully asynchronous memory mover

Cache management during asynchronous memory move operations

Asynchronous memory move across physical nodes with dual-sided communication

Sourcing differing amounts of prefetch data in response to data prefetch requests

Mechanisms for communicating with an asynchronous memory mover to perform AMM operations

Techniques for data prefetching using indirect addressing with offset

Techniques for indirect data prefetching

BURKY WILLIAM E

Processor and method for partially flushing a dispatched instruction group including a mispredicted branch

SHEN XIAOWEI

System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory