Inventor
NGUYEN HUNG T
US51 patents
⚠️ This page may combine multiple inventors who share the name “NGUYEN HUNG T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
APPLIED MATERIALS INC
12 patentsUS8033772B2Oct 11, 2011
Transfer chamber for vacuum processing system
APPLIED MATERIALS INC15 citations93
US7018517B2Mar 28, 2006
Transfer chamber for vacuum processing system
APPLIED MATERIALS INC39 citations93
US6833717B1Dec 21, 2004
Electron beam test system with integrated substrate transfer module
APPLIED MATERIALS INC35 citations92
US6824343B2Nov 30, 2004
Substrate support
APPLIED MATERIALS INC20 citations92
US7735710B2Jun 15, 2010
Substrate support
APPLIED MATERIALS INC10 citations84
US7919972B2Apr 5, 2011
Integrated substrate transfer module
APPLIED MATERIALS INC5 citations73
US7746088B2Jun 29, 2010
In-line electron beam test system
APPLIED MATERIALS INC6 citations73
US7535238B2May 19, 2009
In-line electron beam test system
APPLIED MATERIALS INC5 citations73
US7330021B2Feb 12, 2008
Integrated substrate transfer module
APPLIED MATERIALS INC6 citations73
US7973546B2Jul 5, 2011
In-line electron beam test system
APPLIED MATERIALS INC1 citations62
US7786742B2Aug 31, 2010
Prober for electronic device testing on large area substrates
APPLIED MATERIALS INC2 citations59
US7602199B2Oct 13, 2009
Mini-prober for TFT-LCD testing
APPLIED MATERIALS INC1 citations51
LSI LOGIC CORP
11 patentsUS7028197B2Apr 11, 2006
System and method for electrical power management in a data processing system using registers to reflect current operating conditions
LSI LOGIC CORP27 citations88
US7107433B1Sep 12, 2006
Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof
LSI LOGIC CORP12 citations84
US7085916B1Aug 1, 2006
Efficient instruction prefetch mechanism employing selective validity of cached instructions for digital signal processor and method of operation thereof
LSI LOGIC CORP11 citations84
US6813704B1Nov 2, 2004
Changing instruction order by reassigning only tags in order tag field in instruction queue
LSI LOGIC CORP17 citations84
US6976156B1Dec 13, 2005
Pipeline stall reduction in wide issue processor by providing mispredict PC queue and staging registers to track branch instructions in pipeline
LSI LOGIC CORP11 citations74
US7051146B2May 23, 2006
Data processing systems including high performance buses and interfaces, and associated communication methods
LSI LOGIC CORP5 citations63
US7013382B1Mar 14, 2006
Mechanism and method for reducing pipeline stalls between nested calls and digital signal processor incorporating the same
LSI LOGIC CORP4 citations63
US6922760B2Jul 26, 2005
Distributed result system for high-performance wide-issue superscalar processor
LSI LOGIC CORP2 citations63
US7167939B2Jan 23, 2007
Asynchronous system bus adapter for a computer system having a hierarchical bus structure
LSI LOGIC CORP4 citations61
US6715038B1Mar 30, 2004
Efficient memory management mechanism for digital signal processor and method of operation thereof
LSI LOGIC CORP3 citations60
US6871247B1Mar 22, 2005
Mechanism for supporting self-modifying code in a harvard architecture digital signal processor and method of operation thereof
LSI LOGIC CORP0 citations50
WHITAKER CORP
3 patentsAMP INC
3 patentsABBOTT CARDIOVASCULAR SYSTEMS INC
3 patentsUS9895244B2Feb 20, 2018
Segmented scaffolds and delivery thereof for peripheral applications
ABBOTT CARDIOVASCULAR SYSTEMS INC18 citations90
US9642730B2May 9, 2017
Processes for making crush recoverable polymer scaffolds
ABBOTT CARDIOVASCULAR SYSTEMS INC8 citations82
US9642729B2May 9, 2017
Reducing crimping damage to a polymer scaffold
ABBOTT CARDIOVASCULAR SYSTEMS INC4 citations80
VERISILICON HOLDINGS CAYMAN IS
3 patentsUS7251721B1Jul 31, 2007
Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline
VERISILICON HOLDINGS CAYMAN IS11 citations84
US7231510B1Jun 12, 2007
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof
VERISILICON HOLDINGS CAYMAN IS4 citations62
US7275149B1Sep 25, 2007
System and method for evaluating and efficiently executing conditional instructions
VERISILICON HOLDINGS CAYMAN IS2 citations58
QUALITY SEMICONDUCTOR INC
2 patentsINTUIT INC
2 patentsABBOTT CARDIOVASCULAR SYSTEMS
2 patentsWANG YUNBING
1 patentNGUYEN HUNG T
1 patentSILICON STORAGE TECH INC
1 patentCLEANSEAL SYSTEMS INC
1 patentNGO MICHAEL H
1 patentGILLICK MATTHEW J
1 patentOROSA DENNIS R
1 patentPAPP JOHN E
1 patentVIRGINIA COMMONWEALTH UNIV INTELLECTUAL PROPERTY FOUNDATION
1 patentShowing the top 50 of 51 patents by PatentIndex Score.