Inventor

KIRSCH GRAHAM

GB63 patents

⚠️ This page may combine multiple inventors who share the name “KIRSCH GRAHAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIRSCH GRAHAM

MICRON TECHNOLOGY INC

Distributed processor memory module and method

Data reordering processor and method for use in an active memory device

High density row RAM for column parallel CMOS image sensors

Active memory command engine and method

Single instruction multiple data massively parallel processor systems on a chip and system using same

Method and apparatus for a shift register based interconnection for a massively parallel processor array

Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect

Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner

Data reordering processor and method for use in an active memory device

Distributed processor memory module and method

Method for forming a single instruction multiple data massively parallel processor system on a chip

Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface

System and method for encoding processing element commands in an active memory device

Providing a register file memory with local addressing in a SIMD parallel processor

Providing a register file memory with local addressing in a SIMD parallel processor

Method of constructing a very wide, very fast distributed memory

Data transfer with a bit vector operation device

Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface

Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface

Modified decode for corner turn

Active memory command engine and method

Processing element and method connecting registers to processing logic in a plurality of configurations

Active memory command engine and method

Method and apparatus for a shift register based interconnection for a massively parallel processor array

Active memory processing array topography and method

Method and circuit for normalization of floating point significants in a SIMD array MPP

Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner

Method and circuit for alignment of floating point significants in a SIMD array MPP

Method of constructing a very wide, very fast distributed memory

Host memory interface for a parallel processor

Data transfer with a bit vector operation device

Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface

Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface

Host memory interface for a parallel processor

Flexible results pipeline for processing element

LSI LOGIC CORP

Microprocessor debugging mechanism employing scan interface

Computer system and method for building a hardware description language representation of control logic for a complex digital system

Microprocessor development systems

Processor development systems

Controllable latch/register circuit

KIRSCH GRAHAM

Interest point detection

Image sensor with flexible interconnect capabilities

APTINA IMAGING CORP

High density row RAM for column parallel CMOS image sensors

High density row RAM for column parallel CMOS image sensors

SEMICONDUCTOR COMPONENTS IND LLC

Image sensor with flexible interconnect capabilities

Image sensor with flexible interconnect capabilities

HUGGETT ANTHONY

Method and apparatus providing perspective correction and/or image dewarping

HUGGETT ANTHONY R

Self calibrating stereo camera

LODESTAR LICENSING GROUP LLC

Data transfer with a bit vector operation device

POPE DAVID R

Efficient system and method for face tracking