Inventor

VISWESWARIAH CHANDRAMOULI

US104 patents

⚠️ This page may combine multiple inventors who share the name “VISWESWARIAH CHANDRAMOULI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VISWESWARIAH CHANDRAMOULI

IBM

Method, system, and program product for computing a yield gradient from statistical timing

System and method for correlated process pessimism removal for static timing analysis

System and method for incremental statistical timing analysis of digital circuits

Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices

System and method for incremental statistical timing analysis of digital circuits

System and method for statistical timing analysis of digital circuits

System and method for probabilistic criticality prediction of digital circuits

Method for incorporating noise considerations in automatic circuit optimization

IC chip at-functional-speed testing with process coverage evaluation

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis

Parameter variation tolerant method for circuit design optimization

Method and apparatus for statistical path selection for at-speed testing

Method of optimizing and analyzing selected portions of a digital integrated circuit

Method of efficient gradient computation

Timing optimization driven by statistical sensitivites

Dynamic voltage frequency scaling

Variable accuracy parameter modeling in statistical timing

Modeling multi-patterning variability with statistical timing

Systems and methods for correlated parameters in statistical static timing analysis

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Systems and methods for correlated parameters in statistical static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Performing statistical timing analysis with non-separable statistical and deterministic variations

System and method for statistical timing analysis of digital circuits

Methods for identifying failing timing requirements in a digital design

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage

Methods for conserving memory in statistical static timing analysis

Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits

Method and apparatus for static timing analysis in the presence of a coupling event and process variation

Variable threshold system and method for multi-corner static timing analysis

Affinity-based clustering of vectors for partitioning the columns of a matrix

Method, system, and program product for accommodating spatially-correlated variation in a process parameter

Method of achieving timing closure in digital integrated circuits by optimizing individual macros

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

System and method for efficient analysis of point-to-point delay constraints in static timing

System and method of optimal waveform shaping

KALAFALA KERIM

Method of measuring the impact of clock skew on slack during a statistical static timing analysis

System and method for performing static timing analysis in the presence of correlations between asserted arrival times

BUCK NATHAN C

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Timing closure on multiple selective corners in a single statistical timing run

HEMMETT JEFFREY G

Performing statistical timing analysis with non-separable statistical and deterministic variations

Methods for statistical slew propagation during block-based statistical static timing analysis

GLOBALFOUNDRIES INC

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

VISWESWARIAH CHANDRAMOULI

Yield computation and optimization for selective voltage binning

FOREMAN ERIC A

Systems and methods for correlated parameters in statistical static timing analysis

SINHA DEBJIT

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

BUCK NATHAN

Chip design and fabrication method optimized for profit

LAVIN MARK A

Decentralized dynamically scheduled parallel static timing analysis