Inventor

JAMES-ROXBY PHILIP B

US49 patents

⚠️ This page may combine multiple inventors who share the name “JAMES-ROXBY PHILIP B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAMES-ROXBY PHILIP B

XILINX INC

Bootable programmable logic device for internal decoding of encoded configuration data

Reconfiguration of a programmable logic device using internal control

Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip

Heterogeneous multiprocessor program compilation targeting programmable integrated circuits

Bootable integrated circuit device for readback encoding of configuration data

Control and reconfiguration of data flow graphs on heterogeneous computing platform

Memory arrangement for message processing by a plurality of threads

Using an embedded processor to implement a finite state machine

Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip

Method for message processing on a programmable logic device

Method and apparatus for a programmable interface of a soft platform on a programmable logic device

Method and system for generating a circuit design including a peripheral component connected to a bus

Reconfiguration of a programmable logic device using internal control

Method and apparatus for processing data stored in a memory shared among a plurality of processors

Device with data processing engine array

Pipeline for processing network packets

Thread circuits and a broadcast channel in programmable logic

Method and apparatus for multithreading on a programmable logic device

Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element

Integrated circuit having a routing element selectively operable to function as an antenna

Method of using a hardware library in a programmable logic device

Reconfigurable priority encoding

Control and reconfiguration of data flow graphs on heterogeneous computing platform

Integration of a run-time parameterizable core with a static circuit design

Dynamic adjustment of floating point exponent bias for exponent compression

Converting floating point data into integer data using a dynamically adjusted scale factor

Data processing engine arrangement in a device

Generation of a specification of a network packet processor

Dataflow graph programming environment for a heterogenous processing system

Streaming interconnect architecture for data processing engine array

Methods and circuits for debugging circuit designs

Compilation flow for a heterogeneous multi-core architecture

Heterogeneous multiprocessor platform targeting programmable integrated circuits

Generation of executable threads having source code specifications that describe network packets

Method and apparatus for providing an interface between a programmable circuit and a processor

Method for simulating a processor of network packets

Circuit for modification of a network packet by insertion or removal of a data segment

Methods of implementing embedded processor systems including state machines

Method of and apparatus for enabling a hardware module to interact with a data structure

Lossless compression using subnormal floating point values

Control and reconfiguration of data flow graphs on heterogeneous computing platform

Machines for inserting or removing fixed length data at a fixed location in a serial data stream

JAMES-ROXBY PHILIP B

Methods and systems with transaction-level lockstep

Redundantly validating values with a processor and a check circuit

Transaction-level lockstep

Communicating state data between stages of pipelined packet processor

Method and apparatus for initializing a system configured in a programmable logic device

Method for scheduling a network packet processor

BREBNER GORDON J

Method for message processing on a programmable logic device