Inventor

OISHI KANJI

JP40 patents

⚠️ This page may combine multiple inventors who share the name “OISHI KANJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OISHI KANJI

HITACHI LTD

Synchronous dynamic memory device capable of operating over wide range of operation frequencies

Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively

Semiconductor memory device having redundancy means

Semiconductor memory device having redundancy means

Semiconductor Integrated circuit device for handling low amplitude signals

Multiprocessor cache system having three states for generating invalidating signals upon write accesses

Semiconductor memory device for performing parallel operations on hierarchical data lines

Semiconductor memory

Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register

Multi-processing system and cache apparatus for use in the same

MOS memory

Semiconductor integrated circuit device

Semiconductor device

Semiconductor device

Semiconductor memory including means for noise suppression

Semiconductor integrated circuit device

Semiconductor integrated circuit device

Static memory containing sense amp and sense amp switching circuit

Static memory containing sense AMP and sense AMP switching circuit

ELPIDA MEMORY INC

Semiconductor storage device

Semiconductor memory device and method of testing same

Semiconductor memory

Semiconductor memory device and semiconductor memory device test method

Size-reduced majority circuit

Semiconductor memory device and operating method thereof

Semiconductor storage device

Data inversion circuit and semiconductor device

Duty detection circuit

Semiconductor memory

Semiconductor memory

Slew rate controlling method and system for output data

Fuse circuit and semiconductor device using fuse circuit thereof

Duty detection circuit

Prevention of the propagation of jitters in a clock delay circuit

Semiconductor memory device having a double branching bidirectional buffer

Command generating circuit and semiconductor memory device having the same

NAKAGAWA HIROSHI

Semiconductor device

NEC CORP

Semiconductor memory device with less data transfer delay time

SAKAMOTO TATSUYA

Semiconductor device

KURITA KOUHEI

Voltage level shift circuit and semiconductor device