Inventor
KANAKASABAPATHY SIVANANDA
US23 patents
⚠️ This page may combine multiple inventors who share the name “KANAKASABAPATHY SIVANANDA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS9431399B1Aug 30, 2016
Method for forming merged contact for semiconductor device
IBM31 citations94
US7531367B2May 12, 2009
Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
IBM24 citations92
US10083964B1Sep 25, 2018
Double diffusion break gate structure without vestigial antenna capacitance
IBM10 citations84
US10276452B1Apr 30, 2019
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM13 citations83
US7442647B1Oct 28, 2008
Structure and method for formation of cladded interconnects for MRAMs
IBM11 citations82
US8901667B2Dec 2, 2014
High performance non-planar semiconductor devices with metal filled inter-fin gaps
IBM4 citations73
US10629495B2Apr 21, 2020
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM2 citations72
US7772663B2Aug 10, 2010
Method and apparatus for bitline and contact via integration in magnetic random access memory arrays
IBM3 citations63
US7919379B2Apr 5, 2011
Dielectric spacer removal
IBM5 citations61
US10115724B1Oct 30, 2018
Double diffusion break gate structure without vestigial antenna capacitance
IBM1 citations52
US7935637B2May 3, 2011
Resist stripping methods using backfilling material layer
IBM0 citations42
KANAKASABAPATHY SIVANANDA
5 patentsUS8421139B2Apr 16, 2013
Structure and method to integrate embedded DRAM with finfet
KANAKASABAPATHY SIVANANDA13 citations83
US8753934B2Jun 17, 2014
Structure and method to integrate embedded DRAM with FinFET
KANAKASABAPATHY SIVANANDA4 citations72
US8120946B2Feb 21, 2012
Stacked magnetic devices
KANAKASABAPATHY SIVANANDA2 citations55
US8133746B2Mar 13, 2012
Method for semiconductor gate hardmask removal and decoupling of implants
KANAKASABAPATHY SIVANANDA0 citations51
US8541275B2Sep 24, 2013
Single metal gate CMOS integration by intermixing polarity specific capping layers
KANAKASABAPATHY SIVANANDA0 citations47
BASKER VEERARAGHAVAN S
3 patentsUS8946802B2Feb 3, 2015
Method of eDRAM DT strap formation in FinFET device structure
BASKER VEERARAGHAVAN S2 citations59
US8927365B2Jan 6, 2015
Method of eDRAM DT strap formation in FinFET device structure
BASKER VEERARAGHAVAN S0 citations49
US9064744B2Jun 23, 2015
Structure and method to realize conformal doping in deep trench applications
BASKER VEERARAGHAVAN S0 citations42