Inventor

WEBEL TOBIAS

DE38 patents

⚠️ This page may combine multiple inventors who share the name “WEBEL TOBIAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEBEL TOBIAS

IBM

Predictive on-chip voltage simulation to detect near-future under voltage conditions

Proactive voltage droop reduction and/or mitigation in a processor core

Redundant oscillator distribution in a multi-processor server system

Mitigating voltage droop

Method and apparatus for automatic scan completion in the event of a system checkstop

Method to prevent firmware defects from disturbing logic clocks to improve system reliability

Adaptive power capping in a chip

Proactive voltage droop reduction and/or mitigation in a processor core

Methods and systems for performing test and calibration of integrated sensors

System and method for controlling idle state exits to manage DI/DT issues

Fault tolerant time synchronization mechanism in a scaleable multi-processor computer

Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer

Proactive voltage droop reduction and/or mitigation in a processor core

Low latency data transfer between clock domains operated in various synchronization modes

Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer

Multi nodal computer system and method for handling check stops in the multi nodal computer system

Multi nodal computer system and method for handling check stops in the multi nodal computer system

Dynamic guard band with timing protection and with performance protection

Method to limit the time a semiconductor device operates above a maximum operating voltage

Dynamically optimizing margins of a processor

Adaptive power capping in a chip

Voltage droop reduction in a processor

Fine resolution on-chip voltage simulation to prevent under voltage conditions

Distributed on chip network to mitigate voltage droops

Methods and systems for performing test and calibration of integrated sensors

Distributed on chip network to mitigate voltage droops

Error checking using serial collection of error data

Error checking using serial collection of error data

Voltage droop management through microarchitectural stall events

Multi-layered processor throttle controller

Voltage overshoot management

Dynamic guard band with timing protection and with performance protection

System for performing a serial communication between a central control block and satellite components

BERGMANN TOBIAS

Synchronous clock stop in a multi nodal computer system

CONKLIN CHRISTOPHER R

Updating settings of a processor core concurrently to the operation of a multi core processor system

BECKER DANIEL

Accounting for microprocessor resource consumption

MAGEE JEFFREY A

Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes

BAUR ULRICH

Integrated circuit arrangement for test inputs