Inventor
KAUSHIK SHIVNANDAN D
US32 patents
⚠️ This page may combine multiple inventors who share the name “KAUSHIK SHIVNANDAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
24 patentsUS7882339B2Feb 1, 2011
Primitives to enhance thread-level speculation
INTEL CORP56 citations98
US7191349B2Mar 13, 2007
Mechanism for processor power state aware distribution of lowest priority interrupt
INTEL CORP59 citations98
US7328293B2Feb 5, 2008
Queued locks using monitor-memory wait
INTEL CORP47 citations96
US7117311B1Oct 3, 2006
Hot plug cache coherent interface method and apparatus
INTEL CORP59 citations96
US7146514B2Dec 5, 2006
Determining target operating frequencies for a multiprocessor system
INTEL CORP64 citations94
US7213093B2May 1, 2007
Queued locks using monitor-memory wait
INTEL CORP22 citations93
US8010969B2Aug 30, 2011
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP16 citations92
US7673090B2Mar 2, 2010
Hot plug interface control method and apparatus
INTEL CORP28 citations92
US7493438B2Feb 17, 2009
Apparatus and method for enumeration of processors during hot-plug of a compute node
INTEL CORP15 citations92
US7117396B2Oct 3, 2006
Scalable CPU error recorder
INTEL CORP26 citations92
US6917999B2Jul 12, 2005
Platform and method for initializing components within hot-plugged nodes
INTEL CORP20 citations92
US7627706B2Dec 1, 2009
Creation of logical APIC ID with cluster ID and intra-cluster ID
INTEL CORP22 citations91
US8032681B2Oct 4, 2011
Processor selection for an interrupt based on willingness to accept the interrupt and on priority
INTEL CORP15 citations84
US7822900B2Oct 26, 2010
Apparatus and method for enumeration of processors during hot-plug of a compute node
INTEL CORP10 citations84
US7640384B2Dec 29, 2009
Queued locks using monitor-memory wait
INTEL CORP10 citations84
US7000102B2Feb 14, 2006
Platform and method for supporting hibernate operations
INTEL CORP17 citations84
US7743233B2Jun 22, 2010
Sequencer address management
INTEL CORP15 citations83
US7769938B2Aug 3, 2010
Processor selection for an interrupt identifying a processor cluster
INTEL CORP18 citations82
US7360103B2Apr 15, 2008
P-state feedback to operating system with hardware coordination
INTEL CORP14 citations82
US7761720B2Jul 20, 2010
Mechanism for processor power state aware distribution of lowest priority interrupts
INTEL CORP7 citations74
US6526431B1Feb 25, 2003
Maintaining extended and traditional states of a processing unit in task switching
INTEL CORP10 citations73
US7376775B2May 20, 2008
Apparatus, system, and method to enable transparent memory hot plug/remove
INTEL CORP2 citations60
US9069605B2Jun 30, 2015
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
INTEL CORP1 citations52
US10452403B2Oct 22, 2019
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP0 citations51
WANG HONG
2 patentsHANKINS RICHARD A
2 patentsUS8887174B2Nov 11, 2014
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
HANKINS RICHARD A2 citations61
US8607235B2Dec 10, 2013
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
HANKINS RICHARD A3 citations61