Inventor
BIGBEE BRYANT
US24 patents
⚠️ This page may combine multiple inventors who share the name “BIGBEE BRYANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
14 patentsUS7882339B2Feb 1, 2011
Primitives to enhance thread-level speculation
INTEL CORP56 citations98
US7974416B2Jul 5, 2011
Providing a secure execution mode in a pre-boot environment
INTEL CORP28 citations92
US7810083B2Oct 5, 2010
Mechanism to emulate user-level multithreading on an OS-sequestered sequencer
INTEL CORP25 citations92
US7849465B2Dec 7, 2010
Programmable event driven yield mechanism which may activate service threads
INTEL CORP18 citations83
US7743233B2Jun 22, 2010
Sequencer address management
INTEL CORP15 citations83
US9990206B2Jun 5, 2018
Mechanism for instruction set based thread execution of a plurality of instruction sequencers
INTEL CORP8 citations82
US8028295B2Sep 27, 2011
Apparatus, system, and method for persistent user-level thread
INTEL CORP4 citations74
US6526431B1Feb 25, 2003
Maintaining extended and traditional states of a processing unit in task switching
INTEL CORP10 citations73
US7793111B1Sep 7, 2010
Mechanism to handle events in a machine with isolated execution
INTEL CORP7 citations72
US9459874B2Oct 4, 2016
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations62
US9875102B2Jan 23, 2018
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9766891B2Sep 19, 2017
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9588771B2Mar 7, 2017
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
INTEL CORP1 citations52
US9383997B2Jul 5, 2016
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
WANG HONG
3 patentsUS8719819B2May 6, 2014
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
WANG HONG4 citations83
US8914618B2Dec 16, 2014
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
WANG HONG3 citations62
US9720697B2Aug 1, 2017
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
WANG HONG0 citations51
MCKEEN FRANCIS X
3 patentsUS8522044B2Aug 27, 2013
Mechanism to handle events in a machine with isolated execution
MCKEEN FRANCIS X3 citations60
US8671275B2Mar 11, 2014
Mechanism to handle events in a machine with isolated execution
MCKEEN FRANCIS X0 citations50
US8458464B2Jun 4, 2013
Mechanism to handle events in a machine with isolated execution
MCKEEN FRANCIS X0 citations50