P

Inventor

SETHI PRASHANT

US73 patents
⚠️ This page may combine multiple inventors who share the name “SETHI PRASHANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

35 patents
US7231486B2Jun 12, 2007

General input/output architecture, protocol and related methods to support legacy interrupts

INTEL CORP85 citations98
US6907510B2Jun 14, 2005

Mapping of interconnect configuration space

INTEL CORP79 citations97
US7949794B2May 24, 2011

PCI express enhancements and extensions

INTEL CORP41 citations95
US7036122B2Apr 25, 2006

Device virtualization and assignment of interconnect devices

INTEL CORP57 citations95
US6370633B2Apr 9, 2002

Converting non-contiguous memory into contiguous memory for a graphics processor

INTEL CORP19 citations93
US8010969B2Aug 30, 2011

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

INTEL CORP16 citations92
US7930566B2Apr 19, 2011

PCI express enhancements and extensions

INTEL CORP13 citations92
US7899943B2Mar 1, 2011

PCI express enhancements and extensions

INTEL CORP16 citations92
US7810083B2Oct 5, 2010

Mechanism to emulate user-level multithreading on an OS-sequestered sequencer

INTEL CORP25 citations92
US6600493B1Jul 29, 2003

Allocating memory based on memory device organization

INTEL CORP26 citations91
US6724390B1Apr 20, 2004

Allocating memory

INTEL CORP41 citations89
US6545684B1Apr 8, 2003

Accessing data stored in a memory

INTEL CORP35 citations89
US10048881B2Aug 14, 2018

Restricted address translation to protect against device-TLB vulnerabilities

INTEL CORP10 citations84
US9535838B2Jan 3, 2017

Atomic operations in PCI express

INTEL CORP2 citations84
US9098415B2Aug 4, 2015

PCI express transaction descriptor

INTEL CORP4 citations84
US9032103B2May 12, 2015

Transaction re-ordering

INTEL CORP5 citations84
US9026682B2May 5, 2015

Prefectching in PCI express

INTEL CORP5 citations84
US7716395B2May 11, 2010

Low latency mechanism for data transfers between a media controller and a communication device

INTEL CORP9 citations84
US7490215B2Feb 10, 2009

Media memory system and method for providing concurrent memory access to a plurality of processors through separate translation table information

INTEL CORP8 citations84
US7065597B2Jun 20, 2006

Method and apparatus for in-band signaling of runtime general purpose events

INTEL CORP17 citations84
US7743233B2Jun 22, 2010

Sequencer address management

INTEL CORP15 citations83
US7120711B2Oct 10, 2006

System and method for communicating over intra-hierarchy and inter-hierarchy links

INTEL CORP15 citations83
US9990206B2Jun 5, 2018

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

INTEL CORP8 citations82
US8028295B2Sep 27, 2011

Apparatus, system, and method for persistent user-level thread

INTEL CORP4 citations74
US10691612B2Jun 23, 2020

System and methods exchanging data between processors through concurrent shared memory

INTEL CORP2 citations73
US10509729B2Dec 17, 2019

Address translation for scalable virtualization of input/output devices

INTEL CORP2 citations73
US11321264B2May 3, 2022

Flattening portal bridge

INTEL CORP2 citations71
US10521386B2Dec 31, 2019

USB-C multiple connector support for host and device mode configurations

INTEL CORP2 citations71
US10078608B2Sep 18, 2018

USB-C multiple connector support for host and device mode configurations

INTEL CORP4 citations71
US9003164B2Apr 7, 2015

Providing hardware support for shared virtual memory between local and remote physical memory

INTEL CORP4 citations71
US10754808B2Aug 25, 2020

Bus-device-function address space mapping

INTEL CORP4 citations69
US11513808B2Nov 29, 2022

Automatic switching and deployment of software or firmware based USB4 connection managers

INTEL CORP5 citations68
US6615286B1Sep 2, 2003

Method and apparatus for updating device driver control data

INTEL CORP11 citations65
US10061707B2Aug 28, 2018

Speculative enumeration of bus-device-function address space

INTEL CORP2 citations64
US9442855B2Sep 13, 2016

Transaction layer packet formatting

INTEL CORP1 citations63

AJANOVIC JASMIN

9 patents

CHINYA GAUTHAM

2 patents

DIXON MARTIN G

1 patent

CHINYA GAUTHAM N

1 patent

WANG HONG

1 patent

BAXTER BRENT S

1 patent

Showing the top 50 of 73 patents by PatentIndex Score.