Inventor
LIN JYUH-FUH
TW11 patents
⚠️ This page may combine multiple inventors who share the name “LIN JYUH-FUH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
10 patentsUS9594862B2Mar 14, 2017
Method of fabricating an integrated circuit with non-printable dummy features
TAIWAN SEMICONDUCTOR MFG CO LTD19 citations92
US9436787B2Sep 6, 2016
Method of fabricating an integrated circuit with optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD11 citations84
US9436788B2Sep 6, 2016
Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD11 citations84
US11061317B2Jul 13, 2021
Method of fabricating an integrated circuit with non-printable dummy features
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations73
US10811225B2Oct 20, 2020
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US10431423B2Oct 1, 2019
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US10359695B2Jul 23, 2019
Method of fabricating an integrated circuit with non-printable dummy features
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US10170276B2Jan 1, 2019
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US9552964B2Jan 24, 2017
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9658538B2May 23, 2017
System and technique for rasterizing circuit layout data
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51