Inventor

LIM KHEE YONG

SG36 patents

⚠️ This page may combine multiple inventors who share the name “LIM KHEE YONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIM KHEE YONG

GLOBALFOUNDRIES SG PTE LTD

Image sensor with stacked SPAD and method for producing the same

Methods for fabricating flash memory cells and integrated circuits having flash memory cells embedded with logic

Strap layout for non-volatile memory device

Sensor device and a method for forming the sensor device

Method to form thicker erase gate poly superflash NVM

Methods for fabricating integrated circuits with low, medium, and/or high voltage transistors on an extremely thin silicon-on-insulator substrate

Diode devices and methods of forming diode devices

Diode devices and methods of forming a diode device

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Avalanche photodetectors with a combined lateral and vertical arrangement

Memory cells and methods of forming a memory cell

Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same

Image sensor with reduced capacitance transfer gate

Wrap around phase change memory

Multi-semiconductor layer photodetector and related method

Memory device and a method for forming the memory device

3D high voltage charge pump

Back-gated non-volatile memory cell

Extended drain MOSFETs (EDMOS)

Fin-based nonvolatile memory structures, integrated circuits with such structures, and methods for fabricating same

Wrap around phase change memory

Transistor devices and methods of forming transistor devices

Method to fabricate capacitance-matching FET and related device

Field-effect transistors with airgap spacers

Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same

Selective shielding of ambient light at chip level

Transistor with source-drain silicide pullback

CHARTERED SEMICONDUCTOR MFG

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Composite stress spacer

Spacer-less low-k dielectric processes

Double anneal with improved reliability for dual contact etch stop liner scheme

IBM

Mechanical stress characterization in semiconductor device

Mechanical stress characterization in semiconductor device

LEE YONG MENG

Spacer-less low-K dielectric processes

LIM KHEE YONG

Double anneal with improved reliability for dual contact etch stop liner scheme

TOH ENG HUAT

Compact charge trap multi-time programmable memory