Inventor
SCHMIT HERMAN HENRY
US29 patents
⚠️ This page may combine multiple inventors who share the name “SCHMIT HERMAN HENRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
21 patentsUS9582349B1Feb 28, 2017
Methods and apparatus for detecting memory bit corruption on an integrated circuit
ALTERA CORP7 citations84
US9553762B1Jan 24, 2017
Network-on-chip with fixed and configurable functions
ALTERA CORP11 citations84
US9479456B2Oct 25, 2016
Programmable logic device with integrated network-on-chip
ALTERA CORP15 citations84
US9362913B1Jun 7, 2016
Circuitry for implementing multi-mode redundancy and arithmetic functions
ALTERA CORP7 citations84
US9922157B1Mar 20, 2018
Sector-based clock routing methods and apparatus
ALTERA CORP14 citations83
US9450609B1Sep 20, 2016
Methods and apparatus for embedding an error correction code in memory cells
ALTERA CORP13 citations83
US10523207B2Dec 31, 2019
Programmable circuit having multiple sectors
ALTERA CORP6 citations73
US9692418B1Jun 27, 2017
Pipelined interconnect circuitry with double data rate interconnections
ALTERA CORP4 citations73
US9606573B1Mar 28, 2017
Configurable clock grid structures
ALTERA CORP6 citations73
US9300421B2Mar 29, 2016
Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder
ALTERA CORP6 citations72
US10367745B1Jul 30, 2019
Network-on-chip with fixed and configurable functions
ALTERA CORP1 citations62
US10191661B1Jan 29, 2019
Lutram dummy read scheme during error detection and correction
ALTERA CORP1 citations59
US10367756B2Jul 30, 2019
Programmable logic device with integrated network-on-chip
ALTERA CORP0 citations52
US10141936B2Nov 27, 2018
Pipelined interconnect circuitry with double data rate interconnections
ALTERA CORP0 citations52
US10044344B2Aug 7, 2018
Systems and methods for a low hold-time sequential input stage
ALTERA CORP0 citations52
US9813061B1Nov 7, 2017
Circuitry for implementing multi-mode redundancy and arithmetic functions
ALTERA CORP0 citations52
US9806696B1Oct 31, 2017
Systems and methods for a low hold-time sequential input stage
ALTERA CORP0 citations52
US10678979B2Jun 9, 2020
Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
ALTERA CORP0 citations51
US10289483B2May 14, 2019
Methods and apparatus for embedding an error correction code in storage circuits
ALTERA CORP0 citations51
US9740808B2Aug 22, 2017
Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
ALTERA CORP0 citations51
US9507883B2Nov 29, 2016
Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
ALTERA CORP0 citations51
INTEL CORP
7 patentsUS10187064B1Jan 22, 2019
Systems and methods for routing data across regions of an integrated circuit
INTEL CORP12 citations84
US10055526B1Aug 21, 2018
Regional design-dependent voltage control and clocking
INTEL CORP3 citations71
US11115026B2Sep 7, 2021
Systems and methods for routing data across regions of an integrated circuit
INTEL CORP0 citations62
US11210443B2Dec 28, 2021
Distributed programmable delay lines in a clock tree
INTEL CORP0 citations52
US10587273B2Mar 10, 2020
Systems and methods for routing data across regions of an integrated circuit
INTEL CORP0 citations52
US10303834B2May 28, 2019
Regional design-dependent voltage control and clocking
INTEL CORP0 citations50
US10860760B2Dec 8, 2020
Systems and methods for implementing learned parameter systems on a programmable integrated circuit
INTEL CORP0 citations48