Inventor

SANKARAPANDIAN MUTHUMANICKAM

US77 patents

⚠️ This page may combine multiple inventors who share the name “SANKARAPANDIAN MUTHUMANICKAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANKARAPANDIAN MUTHUMANICKAM

IBM

Integrating and isolating nFET and pFET nanosheet transistors on a substrate

Layer transfer process and functionally enhanced integrated circuits produced thereby

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same

SiCOH hardmask with graded transition layers

DSA grapho-epitaxy process with etch stop material

Vertical transistors with improved top source/drain junctions

Protection of high-K dielectric during reliability anneal on nanosheet structures

Integrating and isolating NFET and PFET nanosheet transistors on a substrate

Channel protection during fin fabrication

Spacer replacement for replacement metal gate semiconductor devices

Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer

Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair

Method for producing self-aligned mask, articles produced by same and composition for same

Contacts and liners having multi-segmented protective caps

Vertical field-effect-transistors having a silicon oxide layer with controlled thickness

Removal of trilayer resist without damage to underlying structure

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Method of forming low-K interlevel dielectric layers and structures

Polycarbosilane buried etch stops in interconnect structures

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Svia using a single damascene interconnect

Nanosheet eDRAM

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Protection of high-K dielectric during reliability anneal on nanosheet structures

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Controlling via critical dimension during fabrication of a semiconductor wafer

Dual work function CMOS devices

Undercut control in isotropic wet etch processes

Phase change memory cell spacer

Metal via structure

Silicon residue removal in nanosheet transistors

Enabling residue free gap fill between nanosheets

Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology

Controlling via critical dimension with a titanium nitride hard mask

Single trench damascene interconnect using TiN HMO

Enabling residue free gap fill between nanosheets

Selective etch chemistry for gate electrode materials

Surface treatment for selective metal cap applications

Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same

Polycarbosilane buried etch stops in interconnect structures

ARNOLD JOHN C

Dual hard mask lithography process

Methods to mitigate plasma damage in organosilicate dielectrics

Methods to mitigate plasma damage in organosilicate dielectrics

Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer

GLOBALFOUNDRIES INC

Method for single fin cuts using selective ion implants

Methods of forming merged source/drain regions on integrated circuit products

INTERMOLECULAR INC

Solution based etching of titanium carbide and titanium nitride structures

FITZSIMMONS JOHN A

Titanium-nitride removal