Inventor · disambiguated record
Kenneth S. Stevens
Also filed as: STEVENS KENNETH S · STEVENS KENNETH SCOTT
17 granted patents·2 pending applications·257 citations·filing 1988–2017
93Inventor score
Files withINTEL CORP6UNIV UTAH RES FOUND6STEVENS KENNETH S5GRANITE MOUNTAIN TECHNOLOGIES1SCHLUMBERGER TECHNOLOGY CORP1
Top patents by PatentIndex Score
19 records- 0185US8065647B2Method and system for asynchronous chip designSTEVENS KENNETH S·Filed 2008·Granted Nov 22, 2011·17 cites·18 claims
- 0282US10310994B2Asynchronous finite state machinesUNIV UTAH RES FOUND·Filed 2017·Granted Jun 4, 2019·5 cites·18 claims
- 0378US4922408AApparatus for multi-processor communicationsSCHLUMBERGER TECHNOLOGY CORP·Filed 1988·Granted May 1, 1990·67 cites·12 claims
- 0472US8239796B2Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verificationSTEVENS KENNETH S·Filed 2010·Granted Aug 7, 2012·3 cites·5 claims
- 0571US9753486B2Clock gating with an asynchronous wrapper cellUNIV UTAH RES FOUND·Filed 2015·Granted Sep 5, 2017·2 cites·19 claims
- 0668US9953120B2Relative timing characterizationUNIV UTAH RES FOUND·Filed 2013·Granted Apr 24, 2018·2 cites·24 claims
- 0767US6557149B2Algorithm for finding vectors to stimulate all paths and arcs through an LVS gateINTEL CORP·Filed 2001·Granted Apr 29, 2003·13 cites·17 claims
- 0866US5931944ABranch instruction handling in a self-timed marking systemINTEL CORP·Filed 1997·Granted Aug 3, 1999·49 cites·23 claims
- 0962US8365116B2Cycle cutting with timing path analysisUNIV UTAH RES FOUND·Filed 2010·Granted Jan 29, 2013·2 cites·18 claims
- 1062US8321825B2Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verificationSTEVENS KENNETH S·Filed 2012·Granted Nov 27, 2012·1 cites·11 claims
- 1158US5948096AApparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytesINTEL CORP·Filed 1997·Granted Sep 7, 1999·36 cites·18 claims
- 1255US6314553B1Circuit synthesis and verification using relative timingINTEL CORP·Filed 1998·Granted Nov 6, 2001·29 cites·29 claims
- 1351US10084434B2Relative timed clock gating cellUNIV UTAH RES FOUND·Filed 2016·Granted Sep 25, 2018·0 cites·12 claims
- 1448US9548736B2Relative timed clock gating cellUNIV UTAH RES FOUND·Filed 2015·Granted Jan 17, 2017·0 cites·2 claims
- 1545US5978899AApparatus and method for parallel processing and self-timed serial marking of variable length instructionsINTEL CORP·Filed 1997·Granted Nov 2, 1999·18 cites·37 claims
- 1643US2013097567A1Cycle cutting with timing path analysisSTEVENS KENNETH S·Filed 2012·Application pending·0 cites
- 1743US2014165022A1Relative timing architectureSTEVENS KENNETH S·Filed 2013·Application pending·0 cites
- 1840US5941982AEfficient self-timed marking of lengthy variable length instructionsINTEL CORP·Filed 1997·Granted Aug 24, 1999·13 cites·18 claims
- 1938US9100315B2Source asynchronous signalingGRANITE MOUNTAIN TECHNOLOGIES·Filed 2013·Granted Aug 4, 2015·0 cites·29 claims
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