Inventor

HESS KEVIN J

US37 patents

⚠️ This page may combine multiple inventors who share the name “HESS KEVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HESS KEVIN J

FREESCALE SEMICONDUCTOR INC

Packaged integrated circuit with enhanced thermal dissipation

Scribe street structure for backend interconnect semiconductor wafer integration

Method of packaging semiconductor devices

Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

Packaged integrated circuit with enhanced thermal dissipation

Integrated circuit die having a copper contact and method therefor

Semiconductor die edge reconditioning

Die level metal density gradient for improved flip chip package reliability

Fused buss for plating features on a semiconductor die

Interconnect for chip level power distribution

Package device having crack arrest feature and method of forming

Packaged integrated circuit

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

Interconnect for improved die to substrate electrical coupling

Cap layer for an aluminum copper bond pad

Fused buss for plating features on a semiconductor die

Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

Integrated circuit package with voltage distributor

PHILLIPS PETROLEUM CO

Ethylene polymers

Apparatus and process for detecting the presence of gel defects in oriented sheets or films based on polarization detection

Ethylene polymer compositions

Ethylene copolymer compositions

HESS KEVIN J

Semiconductor device package

Molded semiconductor package having a filler material

Localized alloying for improved bond reliability

Localized alloying for improved bond reliability

PELLEY PERRY H

Stacked semiconductor die with continuous conductive vias

Stacked semiconductor devices

Stacked semiconductor devices

MCSHANE MICHAEL B

Techniques for reducing inductance in through-die vias of an electronic assembly

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

HUNTSMAN SPEC CHEM CORP

Polyolefin containing polyetheramine modified functionalized polyolefin

JOHNSTON JAMES P

Power lead-on-chip ball grid array package

LEE CHU-CHUNG

Integrated circuit package with voltage distributor

STOCKINGER MICHAEL A

High frequency interconnect pad structure

WENZEL ROBERT J

Packaged integrated circuit using wire bonds