Inventor
NING TAK
US18 patents
⚠️ This page may combine multiple inventors who share the name “NING TAK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS10483368B1Nov 19, 2019
Single crystalline extrinsic bases for bipolar junction structures
IBM6 citations84
US10998444B2May 4, 2021
Stacked FinFET masked-programmable ROM
IBM2 citations73
US10896912B2Jan 19, 2021
Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices
IBM4 citations73
US10636804B1Apr 28, 2020
Stacked FinFET programmable inverter (EPROM)
IBM5 citations73
US10319442B2Jun 11, 2019
Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
IBM2 citations72
US10049742B1Aug 14, 2018
Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
IBM3 citations72
US9806151B2Oct 31, 2017
Biosensor based on heterojunction bipolar transistor
IBM2 citations72
US11476264B2Oct 18, 2022
Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices
IBM0 citations62
US10998419B2May 4, 2021
Single crystalline extrinsic bases for bipolar junction structures
IBM0 citations62
US10896979B2Jan 19, 2021
Compact vertical injection punch through floating gate analog memory and a manufacture thereof
IBM0 citations62
US10504991B2Dec 10, 2019
Biosensor based on heterojunction bipolar transistor
IBM1 citations62
US10170186B1Jan 1, 2019
High-density EEPROM arrays utilizing stacked field effect transistors
IBM1 citations62
US10756097B2Aug 25, 2020
Stacked vertical transistor-based mask-programmable ROM
IBM0 citations52
US10658353B2May 19, 2020
Stacked electrostatic discharge diode structures
IBM0 citations52
US10090290B1Oct 2, 2018
Stacked electrostatic discharge diode structures
IBM0 citations52
US10839909B2Nov 17, 2020
Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array
IBM0 citations51