Inventor
THOMAS AJISH
US4 patents
Patents
4 patentsUS10181000B1Jan 15, 2019
Scheduling parallel processing of multiple partitions for signal electromigration analysis
CADENCE DESIGN SYSTEMS INC9 citations79
US10192012B1Jan 29, 2019
Pseudo-inverter configuration for signal electromigration analysis
CADENCE DESIGN SYSTEMS INC3 citations67
US10769330B1Sep 8, 2020
Partitioning a large circuit model for signal electromigration analysis
CADENCE DESIGN SYSTEMS INC1 citations56
US10235482B1Mar 19, 2019
Exhaustive input vector stimuli for signal electromigration analysis
CADENCE DESIGN SYSTEMS INC1 citations56