Inventor
LEU JIHPERNG
US29 patents
⚠️ This page may combine multiple inventors who share the name “LEU JIHPERNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
27 patentsUS6605549B2Aug 12, 2003
Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
INTEL CORP162 citations99
US6605874B2Aug 12, 2003
Method of making semiconductor device using an interconnect
INTEL CORP359 citations98
US6479391B2Nov 12, 2002
Method for making a dual damascene interconnect using a multilayer hard mask
INTEL CORP88 citations98
US7018918B2Mar 28, 2006
Method of forming a selectively converted inter-layer dielectric using a porogen material
INTEL CORP76 citations97
US6867125B2Mar 15, 2005
Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
INTEL CORP54 citations96
US6998216B2Feb 14, 2006
Mechanically robust interconnect for low-k dielectric material using post treatment
INTEL CORP33 citations93
US6924222B2Aug 2, 2005
Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
INTEL CORP32 citations93
US7727892B2Jun 1, 2010
Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
INTEL CORP16 citations92
US7214594B2May 8, 2007
Method of making semiconductor device using a novel interconnect cladding layer
INTEL CORP19 citations92
US6943121B2Sep 13, 2005
Selectively converted inter-layer dielectric
INTEL CORP43 citations92
US6903461B2Jun 7, 2005
Semiconductor device having a region of a material which is vaporized upon exposing to ultraviolet radiation
INTEL CORP16 citations92
US6734094B2May 11, 2004
Method of forming an air gap within a structure by exposing an ultraviolet sensitive material to ultraviolet radiation
INTEL CORP16 citations92
US7294934B2Nov 13, 2007
Low-K dielectric structure and method
INTEL CORP21 citations88
US7466025B2Dec 16, 2008
Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
INTEL CORP12 citations84
US6743712B2Jun 1, 2004
Method of making a semiconductor device by forming a masking layer with a tapered etch profile
INTEL CORP16 citations84
US7339271B2Mar 4, 2008
Metal-metal oxide etch stop/barrier for integrated circuit interconnects
INTEL CORP9 citations83
US6992391B2Jan 31, 2006
Dual-damascene interconnects without an etch stop layer by alternating ILDs
INTEL CORP12 citations83
US6964919B2Nov 15, 2005
Low-k dielectric film with good mechanical strength
INTEL CORP13 citations82
US6846755B2Jan 25, 2005
Bonding a metal component to a low-k dielectric material
INTEL CORP6 citations74
US7320935B2Jan 22, 2008
Semiconductor device using an interconnect
INTEL CORP6 citations73
US6794755B2Sep 21, 2004
Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement
INTEL CORP11 citations72
US6734118B2May 11, 2004
Dielectric material treatment
INTEL CORP8 citations71
US7164206B2Jan 16, 2007
Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
INTEL CORP8 citations70
US7348283B2Mar 25, 2008
Mechanically robust dielectric film and stack
INTEL CORP5 citations63
US7239019B2Jul 3, 2007
Selectively converted inter-layer dielectric
INTEL CORP2 citations62
US7145245B2Dec 5, 2006
Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate—therein
INTEL CORP4 citations60
US7175970B2Feb 13, 2007
Mechanically robust interconnect for low-k dielectric material using post treatment
INTEL CORP0 citations52