Inventor

KUO YU-TSE

TW46 patents

⚠️ This page may combine multiple inventors who share the name “KUO YU-TSE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO YU-TSE

UNITED MICROELECTRONICS CORP

Static random-access memory (SRAM) cell array and forming method thereof

Memory device

Semiconductor layout structure

Dummy gate technology to avoid shorting circuit

Static random access memory

Layout pattern for 8T-SRAM and the manufacturing method thereof

Static random access memory cell and manufacturing method thereof

Layout pattern of a static random access memory

Layout pattern of a memory device formed by static random access memory

Dummy gate technology to avoid shorting circuit

Method of forming static random-access memory (SRAM) cell array

Static random-access memory (SRAM) cell array

Semiconductor layout pattern and forming method thereof

Ternary content addressable memory unit capable of reducing charge sharing effect

Static random access memory

Static random access memory structure

Layout pattern for static random access memory

Control circuit used for ternary content-addressable memory with two logic units

Layout pattern for static random access memory

Dual port static random access memory (DPSRAM) cell

Spin-orbit torque magnetic random access memory circuit and layout thereof

Static random-access memory (SRAM) cell array

Layout pattern of two-port ternary content addressable memory

Two-port ternary content addressable memory and layout pattern thereof, and associated memory device

Semiconductor device and semiconductor apparatus

Layout pattern of magnetoresistive random access memory

Layout pattern of magnetoresistive random access memory

Layout pattern of magnetoresistive random access memory

Layout of semiconductor memory device

Layout pattern of magnetoresistive random access memory

Memory including non-volatile cells and current driving circuit

Layout configuration for memory cell array

Layout pattern of static random access memory

Ternary content addressable memory and two-port static random access memory

Method of forming static random-access memory (SRAM) cell array

Static random-access memory (SRAM) cell array and forming method thereof

Static random-access memory device

Six-transistor static random access memory cell and operation method thereof

Semiconductor structure

Semiconductor layout structure

Layout pattern of static random access memory and the forming method thereof

Memory device with oxide semiconductor static random access memory and method for operating the same

Semiconductor memory device

Semiconductor memory device

Static random access memory device with keeper circuit

CHUANG MENG-PING

Layout configuration for memory cell array