Inventor
PRUE SARAH C
US3 patents
Patents
3 patentsUS7240306B2Jul 3, 2007
Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing
IBM8 citations71
US7389480B2Jun 17, 2008
Content based yield prediction of VLSI designs
IBM2 citations61
US7661081B2Feb 9, 2010
Content based yield prediction of VLSI designs
IBM1 citations51