Inventor

WANG MEI-YUN

TW220 patents

⚠️ This page may combine multiple inventors who share the name “WANG MEI-YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG MEI-YUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Prevention of contact bottom void in semiconductor fabrication

Method for fabricating self-aligned contact in a semiconductor device

Semiconductor device and manufacturing method thereof

Backside via with a low-k spacer

Backside via with a low-k spacer

Prevention of contact bottom void in semiconductor fabrication

Semiconductor device and method

Metal gate structure cutting process

Forming metal contacts on metal gates

Prevention of contact bottom void in semiconductor fabrication

Isolation features and methods of fabricating the same

Method for source/drain contact formation in semiconductor devices

Semiconductor device and a method for fabricating the same

Method of forming trenches with different depths

Mask-less dual silicide process

Semiconductor device with backside spacer and methods of forming the same

Via-first process for connecting a contact and a gate electrode

Semiconductor device and method for forming the same

Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same

Semiconductor structure with conductive structure

Method for forming fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact

Semiconductor devices with backside via and methods thereof

Semiconductor device and method

Epitaxial source/drain structures for multigate devices and methods of fabricating thereof

Semiconductor devices with backside via and methods thereof

Epitaxial source/drain structure and method

Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same

Method of forming backside power rails

Silicide backside contact

Different via configurations for different via interface requirements

Semiconductor device and method

Parasitic capacitance reduction

Methods of forming air spacers in semiconductor devices

TAIWAN SEMICONDUCTOR MFG

Semiconductor structure including silicide regions and method of making same

Method of forming silicided gate structure

Sidewall coverage for copper damascene filling

One step dual salicide formation for ultra shallow junction applications

Method for forming incompletely landed via with attenuated contact resistance

Methods of manufacturing metal-silicide features

Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors

Multi-step deposition to improve the conformality of ionized PVD films

Method of forming contact plug on silicide structure

Method of forming metal silicide

Eliminate bridging between gate and source/drain in cobalt salicidation

Method of passivating a metal line prior to deposition of a fluorinated silica glass layer

Semiconductor device and formation thereof

Tungsten deposition process with dual-step nucleation

Key-hole reduction during tungsten plug formation

LIN CHEN-TUNG

Methods of manufacturing metal-silicide features

TSAI WEN-CHI

Semiconductor device and method for forming the same